Method and apparatus for DRAM memory performance enhancement
AssigneeApollo Computer, Inc.
InventorsJeffrey D. Kurtze, James Turner
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Abstract
A method and apparatus is disclosed for improving the performance of a digital computer by reducing the latency of read operations and increasing available write bandwidth by utilizing a subset of the address bits which are the same from one operation to the next. A faster cycle type (e.g. page mode or static column) can thereby be employed in the Dynamic Random Access Memory (DRAM) memory by eliminating the DRAM precharge and RAS address portions of the cycle.
Claims9
A fast memory system, comprising
- a static column dynamic random access memory (DRAM);
- a command queue for receiving memory commands and providing DRAM address signals in response to said memory commands;
- a RAM control means for receiving said DRAM address signals and issuing DRAM control signals to said DRAM;
- and
- address compare means for comparing successive DRAM address signals and providing a RAM control signal to said RAM control mans when a select portion of said DRAM address signals are equal, wherein
- the RAM control signal is asserted for a new command without providing a different subsequent row address signal.
A method of high speed static column dynamic random access memory data transfer, comprising the steps of:
- issuing a first read command for writing data into said DRAM for data having a first address comprising a plurality of signals;
- issuing a second read command for reading data from said DRAM for data having a second address comprising a plurality of signals;
- and
- comparing said first and second address;
- starting said second read operation associated with said read command before said first read operation associated with said write command when the data provided by said DRAM in response to said read operation does not affect said first read operation and when said first and second addresses share at least a common portion of said address signals.
A method a high speed static column dynamic random access memory data transfer, comprising the steps of:
- entering a plurality of commands into a queue including a respective plurality of queue locations, said plurality of commands each including a row address select field;
- advancing each of said plurality of commands from each of said respective plurality of queue locations to a respective plurality of next queue locations and toward a next command to be executed location, for subsequent execution by a memory control means including a state machine;
- comparing said row address select field of a current command being executed, with said row address select field of a next command to be executed to generate a result;
- outputting said result to said memory control means;
- affecting a sequence of execution of said state machine in accordance with said result;
- and
- performing memory operations in accordance with control signals generated by said memory control means in response to said sequence of execution of said state machine.
Dependencies are inferred from the claim text.