Neural network implementation of a binary adder
AssigneeSamsung Electronics Co., Ltd.
InventorHo-sun Jeong
Life of this patent
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Abstract
A binary adder is provided for adding-processing in a high speed parallel manner two N bit binary digits. The binary adder is implemented using neural network techniques and includes a number of amplifiers corresponding to the N bit output sum and a carry generation from the result of the adding process; an augend input-synapse group, an addend input-synapse group, a carry input-synapse group, a first bias-synapse group a second bias-synapse group an output feedback-synapse group and inverters. The binary adder is efficient and fast compared to conventional techniques.
Claims12
A binary adder for adding-processing in a parallel manner two N bit binary digits, an augend and an addend, and a carry in and outputting an N bit output sum and a carry out comprising:
- (N+1) output buffer amplifiers corresponding to the N bit output sum and the carry out resulting from said adding-processing;
- augend input-synapse group means for coupling a first power source voltage to an input line of said each output buffer amplifier, according to a value of the augend, with a connecting weight value corresponding to each binary bit value of the N bit binary augend input;
- addend input-synapse group means for coupling the first power source voltage to the input line of said each output buffer amplifier, according to the value of the addend, with a connecting weight value corresponding to each binary bit value of the binary addend input;
- carry input-synapse group means for coupling the first power source voltage to the input line of said each output buffer amplifier, according to a value of the carry in, the with a connecting weight value of a reference weighting value according to the carry input;
- first bias-synapse group means for coupling a second power source voltage to the input line of said each output buffer amplifier with the connecting weight value of a binary value of said output sum and carry bit;
- second bias-synapse group means for coupling said first power source voltage to the input line of said each output buffer amplifier teach with a connecting weight value of a reference weighting value;
- an output feedback-synapse group means for coupling said second power source voltage to the input line of each lower bit output buffer amplifier, according to the value of each upper bit output buffer amplifier, with a connecting weight value corresponding to the binary output value each upper bit output buffer amplifier;
- and
- means for inverting outputs of said output buffer amplifiers.
A binary adder for adding input of two N bit binary digits, addend and augend, and a carry in, and outputting an N bit sum and a carry out comprising:
- (N+1) output buffer amplifiers corresponding to the N bit sum and the carry out;
- input-synapse group means for coupling a first power source voltage to an input line of said each output buffer amplifier, according to the value of the input;
- bias-synapse group means for biasing the input line of said each output buffer amplifier to a predetermined voltage level;
- output feedback-synapse group means for coupling a second power source voltage to the input line of each lower bit output buffer amplifier, according to the value of each upper bit output buffer amplifier, with a connecting weight value corresponding to the binary output value of each upper bit output buffer amplifier;
- and
- means for inverting outputs of said output buffer amplifiers.
Dependencies are inferred from the claim text.