Process of making BiCMOS devices having closely spaced device regions

A method of forming at least one bipolar and two complementary metal oxide semiconductor transistors (BICMOS) comprising the steps of:

• providing a body of semiconductor material including first, second, and third electrically isolated device regions, said first and second device regions adjacent each other and of opposite conductivity types;
• forming first, second, and third studs over said first, second and third device regions, respectively, such that said first and second studs bisect said first and second device regions;
• using said first and second studs as masks to form first and second doped regions adjoining opposite sides of said first and second studs in each of said first and second device regions, respectively, each of said first and second doped regions of opposite conductivity type to its associated device region;
• forming first, second, and third insulating sidewalls on said first, second, and third studs, respectively;
• forming a layer of conductive material generally conformally over said semiconductor body, said studs, and said sidewalls to a depth at least equal to the height of said sidewalls;
• planarizing by chemically-mechanically polishing said layer of conductive material to a height generally equal to or less than the height of said sidewalls;
• and
• patterning the planarized layer of conductive material, whereby to form spaced apart first and second contacts overlying said first and second doped regions in each of said first and second device regions, respectively, and an extrinsic base contact overlying said third device region;
• removing said third stud while leaving the sidewall associated with said third stud to expose a portion of said third device region;
• using said third sidewall as a mask to form, by out-diffusion from a solid dopant source, an intrinsic base region of opposite conductivity type to said third device region in the surface of said third device region;
• and
• forming a vertical bipolar transistor in said third device region and first and second insulated gate transistors in said first and second device regions, respectively.