Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuit

A semiconductor integrated circuit device formed on a single chip, said semiconductor integrated circuit device comprising:

• a first memory circuit for reading and writing data;
• a second memory circuit for reading and writing data;
• a first logic circuit for generating a first address signal for the read operation of said first memory circuit;
• a second logic circuit for generating a second address signal for the read operation of said second memory circuit;
• a third logic circuit for generating a third address signal for the write operation of said first and second memory circuits;
• a fourth logic circuit for selectively supplying one of said first and third address signals to said first memory circuit;
• a fifth logic circuit for selectively supplying one of said second and third address signals to said second memory circuit;
• a first signal line connected between said first memory circuit and said fourth logic circuit;
• a second signal line connected between said second memory circuit and said fifth logic circuit;
• a third signal line connected between said first logic circuit and said fourth logic circuit, for supplying said first address signal to said fourth logic circuit;
• a fourth signal line connected between said third logic circuit and said fourth logic circuit, for supplying said third address signal to said fourth logic circuit;
• a fifth signal line connected between said second logic circuit and said fifth logic circuit, for supplying said second address signal to said fifth logic circuit;
• and
• a sixth signal line connected between said third logic circuit and said fifth logic circuit, for supplying said third address signal to said fifth logic circuit;
• wherein the length of said third, fourth, fifth and sixth signal lines is substantially the same.