Programmable delay line utilizing measured actual delays to provide a highly accurate delay

A method of operating a programmable delay circuit to impose a selected delay on an electronic signal, said delay circuit comprising a plurality of delay stages, each of said delay stages including first and second signal paths for said electronic signal, said first signal path having a reference delay, said second signal path having said reference delay plus an additional delay, said method comprising the steps of:

• providing said plurality of delay stages, each of said second signal paths having a substantially fixed but not precisely known additional delay;
• measuring the actual additional delay through each of said second signal paths;
• and
• selecting, based on the additional delays obtained in said measuring step, the first or second signal path through each of said delay stages.

A method of imposing a selected delay on an electronic signal comprising the steps of:

• providing a plurality N of delay stages, each of said N delay stages including first and second signal paths for said electronic signal, said first signal path having a minimum delay, said second signal path having said minimum
• delay plus an additional substantially fixed delay equal to approximately a power of 2 times a minimum delta delay,
• measuring the total delay through said first signal paths;
• measuring the delay through each individual one of said second signal paths;
• calculating the additional delay through each individual one of said second signal paths;
• determining which combination of said second signal paths will provide a total additional delay closest to said selected delay;
• and
• directing said electronic signal through the second signal paths selected in said determining step.

A delay circuit for imposing a selected delay on an electronic signal, comprising:

• a plurality of delay stages, each having at least one substantially fixed but not precisely known delay;
• means for directing said electronic signal through selected ones of said delay stages;
• means for measuring the actual signal delay through each of said delay stages;
• and means for selecting, based on the actual signal delays obtained in said measuring step, the delay stages through which said electronic signal is directed.

A programmable delay circuit for imposing a selected delay on an electronic signal, said delay circuit comprising:

• a plurality of delay stages, each of said delay stages including first and second signal paths for said electronic signal, said first signal path having a reference delay, said second signal path having said reference delay plus a substantially fixed but not precisely known additional delay;
• means for measuring the actual additional delay through each individual one of said second signal paths;
• and
• means for selecting, based on the additional delays obtained by said measuring means, the first or second signal path through each of said delay stages.

A delay circuit for imposing a selected delay on an electronic signal comprising:

• a plurality N of delay stages, each of said N delay stages including first and second signal paths for said electronic signal, said first signal path having a minimum delay, said second signal path having said minimum delay plus an additional, substantially fixed delay equal to about a power of two times a minimum delta delay;
• means for measuring the total delay through said first signal paths;
• means for measuring the individual delay through each of said second signal paths;
• means for calculating the additional delay through each of said second signal paths;
• means for determining which combination of said second signal paths will provide an additional delay closest to said selected delay;
• and
• means for directing said electronic signal through the second signal paths selected by said determining means.