Method for parallel testing of semiconductor devices
AssigneeMotorola, Inc.
InventorHugh W. Littlebury
Life of this patent
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Abstract
A method of testing unpackaged integrated circuits using a tester which is capable of testing a plurality of memories in parallel is provided. A membrane test head having a plurality of probe bumps thereon is provided wherein the probe bumps are coupled to the tester by microstrip transmission lines formed on the membrane test head. The semiconductor memory has a plurality of contact pads thereon which are coupled to the probes. In this manner, a plurality of semiconductor memories can be tested in wafer form. Alternatively, individual semiconductor memory chips can be mounted on a receiver plate and tested individually or in parallel by moving the receiver plate so that the contact pads couple to the probes.
Claims8
A method of testing a plurality of semiconductor memory chips which are separated from a semiconductor wafer in which they were formed in parallel comprising the steps of:
- providing a tester which is capable of parallel testing memory devices;
- providing a flexible membrane having a plurality of probe bumps which are coupled to the tester;
- placing the individual memory chips on a receiver plate, wherein the receiver plate has a plurality of vacuum ports for holding the memory chips;
- testing access time of the plurality of memory chips in parallel;
- and storing information relating to location of memory chips which pass the test.
A method for testing a plurality of integrated circuits which are separated from a semiconductor wafer in which they were formed, wherein each of the integrated circuits has a plurality of contact pads for electrical connection to the integrated circuit, the method comprising the steps of:
- providing a receiver plate having a vacuum port for each of the plurality of integrated circuits, wherein the vacuum port is sized to hold one of the integrated circuits;
- providing a well in the receiver plate surrounding each of the vacuum ports, wherein the well is sized to prevent substantial movement of the integrated circuit;
- providing a membrane probe having a plurality of probe bumps formed on one side of a flexible membrane, wherein the probe bumps are electrically coupled to a tester;
- placing each of the integrated circuits individually on the receiver plate covering one vacuum port;
- applying a vacuum to each of the vacuum ports;
- moving the receiver plate and/or the membrane probe so that the probe bumps couple to each of the plurality of contact pads of the plurality of integrated circuits;
- and testing the plurality of integrated circuits.
Dependencies are inferred from the claim text.