Apparatus for low skew system clock distribution and generation of 2X frequency clocks
AssigneeApollo Computer, Inc.
InventorsScott Markinson, Michael Schuster, Thomas Hogan
Life of this patent
Estimating the term…
Abstract
A clock generation circuit on each circuit board of a computer system and which removes board-to-board system skew in clock signal distribution. A phase-locked loop is employed to maintain synchronization between the system reference clock signal distributed to each board and the outputs of the distribution gate array in the generation circuit on each board. A 2X frequency clock is provided by combining the clock signal with a delayed version of itself. A second order loop is employed to monitor the duty cycle of the 2X frequency clock and to adjust the duty cycle of the regular frequency clock to provide cycle-to-cycle symmetry for the 2X frequency clock.
Claims9
Apparatus for generation of a plurality of synchronized clock signals on a computer system circuit board from a reference clock signal comprising:
- means for receiving a reference clock signal;
- means for providing a clock signal whose frequency may be varied in response to a control signal;
- means, receiving said clock signal, for providing a plurality of clock output signals having a selected phase relationship therebetween and having a delay from said reference clock signal;
- phase-locked loop means receiving said reference clock signal and a selected one of said plurality of clock output signals, for providing a control signal to said clock signal providing means, for varying the frequency of said plurality of clock output signals, to maintain a phase relationship between said plurality of clock output signals and said reference clock signal and to compensate for said delay;
- frequency multiplier means, receiving said clock signal, for providing an output signal at a frequency being a multiple of said clock signal, and comprising plural clock pulses each having a specified duty cycle relative to said clock signal;
- and
- duty cycle control means for controlling the duty cycle of each of said plural clock pulses.
Apparatus for distributing clock signals in a computer system comprising:
- means for generating a reference clock signal;
- and
- a plurality of duplication means, receiving said reference clock signal, for generating a plurality of clock output signals having a selected phase relationship with said reference clock signal, each of said duplication means including:
- means for receiving said reference clock signal;
- means for generating a clock signal whose frequency may be varied in response to a control signal;
- means, receiving said clock signal, for providing a plurality of clock output signals having a selective phase relationship therebetween, and having a delay from said reference clock signal;
- and
- phase-locked loop means receiving said reference clock signal and a selected one of said plurality of clock output signals, for providing a control signal to said clock signal generating means, for varying the frequency of said clock signal to maintain a phase relationship between said plurality of clock output signals and said reference clock signal, and to compensate for said delay.
Dependencies are inferred from the claim text.