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US 5,005,120 AGranted
Compensating time delay in filtering signals of multi-dimensional reconvigurable array processors
AssigneeLSI Logic Corporation
InventorPeter A. Ruetz
Life of this patent
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Abstract
Apparatus for an array of digital signal processors that can be reconfigured as a one-dimensional or as a two-dimensional array; and method and apparatus for compensating for inconsistent time delays in signals processed by n-dimensional arrays of signal processors.
Claims10
A reconfigurable signal processing module comprising:
- a first module input port (X.1) for receiving a first digital signal stream (A.1=a.sub.1,1 a.sub.1,2 . . . a.sub.1,n.1) having sequential data components (a.sub.1,1 a.sub.1,2 . . . a.sub.1,n.1) representing a first number n.1>1 of sample values;
- a second module input port (X.2) for receiving a second digital signal stream (A.2=a.sub.2,1 a.sub.2,2 . . . a.sub.2,n.2) having sequential data components (a.sub.2,1 a.sub.2,2 . . . a.sub.2, n.2) representing a second number n.2>1 of sample values;
- a first chain of register means (P.sub.1,1 P.sub.1,2 . . . P.sub.1,n.1), having a first end coupled to the first module input port (X.1), for receiving and storing the data components (a.sub.1,1 a.sub.1,2 . . . a.sub.1,n.1) of the first digital signal stream (A.1) and for outputting predesignated stored ones of said data components (a.sub.1,1 a.sub.1,2 . . . a.sub.1,n.1) in parallel onto a corresponding number of first-chain tap lines;
- first multiplexer means, having first and second selectable multiplexer input ports and a first multiplexer output port, for outputting signals appearing on a selected one of the first and second multiplexer input ports, the first multiplexer input port being coupled to a preselected one or more of the first-chain tap lines and the second multiplexer input port being coupled to the second module input port (X.2);
- a second chain of register means (P.sub.2,1 P.sub.2,2 . . . P.sub.2,n.2), having a first end coupled to the first multiplexer output port, for receiving and storing, during a first mode of the first multiplexer means, each of the data components (a.sub.2,1 a.sub.2,2 . . . a.sub.2,n.2) of the second digital signal stream (A.2) and for outputting predesignated ones of said data components (a.sub.2,1 a.sub.2,2 . . . a.sub.2,n.2) in parallel onto a corresponding number of second-chain tap lines, the second chain of register means being further for receiving and storing, during a second mode of the first multiplexer means, a plurality of first-chain-stored data components transmitted from the preselected one or more first-chain tap lines and for outputting predesignated ones of said first-chain-stored data components in parallel onto a corresponding number of second-chain tap lines, the first mode of the first multiplexer means being one in which the first multiplexer input port is coupled to the first multiplexer output port, the second mode of the first multiplexer means being one in which the second multiplexer input port is coupled to the first multiplexer output port;
- and
- function generating means, having function input lines coupled to predetermined ones of the first-chain and second-chain tap lines, for receiving as input parameter signals of a predetermined signal processing function, preselected ones of the shifted data components (a.sub.1,1, a.sub.1,2, . . . , a.sub.1,n.1 and a.sub.2,1, a.sub.2,2, . . . a.sub.2,n.2) and for outputting on a function output bus of the function generating means, a digital function signal which is produced according to said signal processing function.
4 more elements
A digital signal processing module comprising:
- first and second module input ports for receiving serial data signals generated outside the module;
- first and second tapped shift register means, each shift register means having an input end, an output end and a series of data storing means interposed between its input and output ends for shifting and storing data signals received at its input end, where the input end of the first shift register means is coupled to the first module input port;
- multiplexer means having a first multiplexer input port coupled to the output end of the first tapped shift register means, a second multiplexer input port coupled to the second module input port and a multiplexer output port coupled to the input end of the second tapped shift register means for selectively coupling the input end of the second tapped shift register means to one of the multiplexer input ports;
- wherein each of said first and second shift register means has tap points provided at output sides of its data storing means for outputting signals representative of the data stored therein;
- where the module further includes
- processor means coupled to the tap points of the first and second tapped shift register means for processing the signals output therefrom;
- wherein said processor means has a processor output port for outputting a result signal which is a function of the signals produced at the tap points of the first and second shift register means;
- and
- where the module further includes:
- result combining means for combining said result signal with a partial result signal generated externally of said module;
- and
- pipeline register means, coupled to an output port of the result combining means, for temporarily storing a combined result signal produced by the result combining means.
9 more elements
Dependencies are inferred from the claim text.