Implantable N-phasic defibrillator output bridge circuit

An implantable defibrillation system for delivering mono-phasic, multi-phasic, and sequential defibrillation pulses to a heart via a pair of electrodes implanted on or about the heart, said system comprising:

• an output circuit comprising capacitor means for storing a predetermined voltage, first and second switching means both connected to said capacitor means and capable of being triggered to active conditions;
• a ground return terminal;
• first and second electrode lead terminals connected, respectively to said first and second switching means and to said pair of electrodes;
• third and fourth switching means for selectively connecting said first and second electrode lead terminals, respectively, to said ground return terminal when triggered to active conditions;
• a control circuit for selectively triggering said first and said third switching means to said active conditions for allowing voltage stored by said capacitor means to discharge through said first and second electrode lead terminals in a first polarity, and triggering said second and fourth switching means to said active conditions for allowing voltage stored by said capacitor means to discharge through said first and second electrode lead terminals in a second polarity opposite to said first polarity.

An implantable defibrillation system for delivering mono-phasic, multi-phasic and sequential defibrillation pulses to a heart via a pair of discharge electrodes implanted on or about the heart, said system comprising:

• sensing electrode means mounted on or about the heart;
• arrhythmia sensing means connected to said sensing electrode means for detecting an arrhythmia of the heart;
• an output circuit comprising capacitor means for storing a predetermined voltage;
• first and second switching means connected to said capacitor means and said discharge electrodes, and capable of being triggered to active conditions;
• a ground return terminal first and second electrode lead terminals connected, respectively, to said first and second switching means and to said pair of electrodes;
• third and fourth switching means for selectively connecting said first and second electrode lead terminals, respectively, to said ground return terminal when triggered to active conditions;
• control means for selectively triggering said first and said third switching means to said active conditions for allowing voltage stored by said capacitor means to discharge through said first and second electrode lead terminals in a first polarity, and triggering said second and fourth switching means to said active conditions for allowing voltage stored by said capacitor means to discharge through said first and second electrode lead terminals in a second polarity opposite to said first polarity.