US 4,998,242 A · Virtual tributary cross connect switch and switch network utilizing the same

Abstract

Switching components and switching networks utilizing a plurality of identical switching components are provided for cross-connecting virtual tributaries of a plurality of substantially SONET formatted signals. The switching components each receive at least one SONET formatted signal and disassemble the signal into its virtual tributary (VT) payload components while marking the V5 byte. The VT data is buffered and switched in phase, time, and space to effect the cross-connect onto SONET signal generating output buses which are synchronously clocked buses running through the components. The space switch is essentially a non-blocking switch matrix. The time switch is a comparison means associated with each incoming VT which compares the VT destination of the data in the buffer to a virtual tributary time indication based on the phase of the synchronous clocked output buses. When the bus phase is indicative of the VT destination of the data, the data is sent to the output bus dictated by the space switch connection. Phase switching is obtained by determining the difference in phase of the incoming VT as defined by the tagged V5 byte and the phase of the synchronous clocked output bus. The phase difference permits a VT frame pointer to be correctly generated. To establish component and system operation and timing, a system bit clock and multiframe clock are provided, with the internal clock of each component in a network chain being advanced one bit clock relative to its adjacent lower component.

Claims35

Dependent claims

A switch component for cross-connecting a plurality of virtual tributaries of at least one substantially SONET formatted data signal to generate at least one other substantially SONET formatted data signal, said switch component comprising:

(a) at least one data receiving means, each data receiving means having means for receiving a substantially SONET formatted data signal, means for disassembling said substantially SONET formatted data signal into its virtual tributary payloads, and means for recognizing and tagging bytes indicative of the phase of said virtual tributary payloads;
(b) buffer means for each virtual tributary of said received substantially SONET formatted data signal, for buffering virtual tributary payload data received from said receiving means;
(c) a plurality of time synchronous clocked output buses on which are generated said substantially SONET formatted data signals being generated;
(d) pointer calculation means associated with each buffer means, each pointer calculation means including means for determining via said tagged bytes a phase difference between the phase of a virtual tributary payload received in said buffer means and the phase of the virtual tributaries of said SONET formatted data signal being generated, and means for generating a pointer indicative of said phase difference;
(e) non-blocking space switching means for coupling said buffer means to any of said time synchronous clocked output buses;
and
(f) time switching means associated with each buffer means for comparing a virtual tributary destination indication for said virtual tributary payload data in said buffer means with a virtual tributary time indication based on the phase of the synchronous clocked output buses, and for writing virtual tributary payload data stored in said buffer means onto one of said output buses as dictated by said non-blocking space switching means when said destination indication and said time indication correspond.

4 more elements

A switch network for cross-connecting a plurality of virtual tributaries of a plurality of substantially SONET formatted data signals to generate a plurality of other substantially SONET formatted data signal, said switch network comprising:

(a) a plurality of chained switch components, each switch component comprising
(1) at least one data receiving means, each data receiving means having means for receiving a substantially SONET formatted data signal, means for disassembling said substantially SONET formatted data signal into its virtual payloads, and means for recognizing and tagging bytes indicative of the phase of said virtual tributary payloads,
(2) buffer means for each virtual tributary of said received substantially SONET formatted data signal, for buffering virtual tributary payload data received from said receiving means,
(3) a plurality of time synchronous clocked output buses on which are generated said substantially SONET formatted data signals being generated;
(4) pointer calculation means associated with each buffer means, each pointer calculation means including means for determining via said tagged bytes a phase difference between the phase of a virtual tributary payload received in said buffer means and the phase of the virtual tributaries of said SONET formatted data signal being generated, and means for generating a pointer indicative of said phase difference,
(5) non-blocking space switching means for coupling said buffer means to any of said time synchronous clocked output buses, and
(6) time switching means associated with each buffer means for comparing a virtual tributary destination indication for said virtual tributary payload data in said buffer means with a virtual tributary time indication based on the phase of the synchronous clocked output buses, and for writing virtual tributary payload data stored in said buffer means onto one of said output buses as dictated by said non-blocking space switching means when said destination indication and said time indication correspond,
where each of said plurality of output buses is common to each of said plurality of chained switching components to cause said switching components to be chained;
(b) clock means for providing at least a system bit clock signal to at least one of said switching components, wherein said plurality of synchronous clocked output buses are clocked according to said system bit clock signal;
and
(c) offset means for causing a multiframe clock signal which indicates phases of said synchronous clocked output buses obtained at a first switch component in said chain of switch components to be (n-1)x system bit clock signals ahead of a multiframe clock signal received at an n'th switch component in said chain of switch components, where x is a predetermined value, and n is an integer.

8 more elements

Dependencies are inferred from the claim text.

Virtual tributary cross connect switch and switch network utilizing the same

Life of this patent

Virtual tributary cross connect switch and switch network utilizing the same

Life of this patent

Abstract

Claims35