High sensitivity miniature pressure transducer

A method for fabricating semiconductor diaphragms adapted for use in transducer apparatus, comprising the steps of:

• pattering by masking a thin semiconductor wafer on opposing planar sides thereof to define spaced apart diaphragm areas;
• etching the semiconductor wafer a first time to remove exposed semiconductor material to a desired depth to define a setback gap;
• removing the mask;
• and
• etching the semiconductor wafer on both sides a second time to uniformly remove semiconductor material to a depth for achieving a desired diaphragm thickness substantially independently of said setback gap.

A method for fabricating a semiconductor material to provide a plurality of uniform diaphragms, comprising the steps of:

• patterning opposing surfaces of a semiconductor wafer with a mask to define a plurality of diaphragm areas;
• etching both sides of the semiconductor wafer at the patterned areas to define a desired setback depth;
• removing the etch mask;
• and
• micromachining both sides of the semiconductor wafer to achieve a desired diaphragm thickness and to provide semiconductor support areas surrounding each said diaphragm with a surface adapted for electrostatic sealing.

A method for fabricating transducer diaphragms, comprising the steps of:

• forming a bilayer wafer of semiconductor material having a p-type material layer and an n-type material layer;
• removing one said material layer to form a thin semiconductor layer;
• patterning by masking said thin layer to define diaphragm areas;
• etching said thin layer to form a setback gap;
• removing said patterning mask;
• and
• uniformly etching said unmasked thin layer until a desired diaphragm thickness is achieved.

A method for fabricating diaphragms adapted for use in transducer apparatus, comprising the steps of:

• masking a wafer of material to define diaphragm areas;
• processing said wafer to form thin diaphragm areas and thicker areas peripheral to each said diaphragm area;
• and
• processing said wafer to form a rigid support area to said thin wafer for handling, said rigid support being thicker than said areas peripheral to said diaphragms to thereby provide said wafer with rigidity for handling purposes.

A processed wafer, comprising:

• a wafer having a plurality of areas defining diaphragms;
• a plurality of areas circumscribing said diaphragm areas which are electrostatically sealable to other material surfaces;
• and
• a support rim circumscribing said wafer, said rim being thicker than the areas circumscribing the diaphragm areas to enhance rigidity thereof.

A method for processing a reinforced semiconductor wafer, comprising the steps of:

• forming an epitaxial semiconductor layer of a first conductivity type on a semiconductor substrate wafer of a second conductivity type;
• masking areas of the substrate wafer desired to be etch protected and masking substantially the entire surface area of the epitaxial layer, thereby defining a support structure to said wafer;
• removing the unmasked areas of the substrate wafer until the epitaxial first type conductivity semiconductor material is exposed on the etched face;
• and
• processing said first conductivity type semiconductor layer for forming elements therein.

A transducer, comprising:

• a conductive capacitor plate;
• a semiconductor diaphragm defining a deflectable capacitor plate spaced apart from said fixed capacitor plate;
• and
• a support structure encircling said semiconductor diaphragm and attached thereto for maintaining said deflectable diaphragm radially tensioned a predefined amount.

A multiple transducer structure, comprising:

• a top support substrate;
• a bottom support substrate;
• a semiconductor wafer having a plurality of recessed areas defining diaphragms, said wafer being sandwiched between said top and bottom support substrates;
• a tension in each said diaphragm;
• and
• an electrostatic seal substantially circumscribing each said diaphragm to said top and bottom support substrates.

A method for fabricating a pretensioned diaphragm, comprising the steps of:

• fabricating a diaphragm structure from a first type of material;
• fabricating a support structure from a different second type of material;
• changing the temperature of said first and second types of material such that each said material undergoes a different dimensional change;
• and
• fixing said diaphragm structure to said support structure and allowing said composite structure to return to a quiescent temperature such that said diaphragm remains in tension.

A method for tensioning a diaphragm, comprising the steps of:

• sandwiching together a support material and a diaphragm material;
• applying an electrical potential to said sandwiched structure such that an electric field is formed therein and a substantially permanent movement of ions occurs in one or the other of said materials such that said diaphragm experiences a radial stress;
• and
• fixing said support material to said diaphragm material such that said radial stress in said diaphragm is maintained.

A method for fabricating tensioned diaphragms, comprising the steps of:

• forming a plurality of thin diaphragms in a semiconductor wafer;
• forming a rim around said wafer with material having a thermal expansion characteristic different than that of said semiconductor wafer;
• and
• changing the temperature of the rimmed wafer such that said rim expands to an extent greater than the wafer material to thereby form a tension in each said diaphragm.

A method for tensioning a diaphragm, comprising the steps of:

• utilizing a diaphragm material having a thermal expansion property in an operating temperature range and a thermal expansion property in a fabrication temperature range;
• utilizing a support material having a given thermal expansion property substantially the same as that of said diaphragm material in the operating temperature range, and a thermal expansion property different than that of the diaphragm material in said fabrication temperature range;
• changing the temperature of said diaphragm material and of said support material to a fabrication temperature and fixing said diaphragm to said support material;
• and
• again changing the temperature of the composite diaphragm material and said support material so that said diaphragm material contracts more than said support material to thereby impart a tension to said diaphragm.

A transducer structure, comprising:

• a top insulator substrate;
• a capacitor plate;
• a bottom insulator substrate;
• the semiconductor wafer having a diaphragm, said wafer being electrostatically bonded between said top and bottom insulator substrates;
• and
• a conductive sealing grid network adjacent a top surface of said top substrate and a conductive sealing grid network adjacent a bottom side of said bottom insulator substrate such that a voltage can be applied under predefined temperature conditions to both said sealing grid networks such that an electrostatic seal is effected on opposing wafer surfaces and circumferentially around said diaphragm.

A transducer structure, comprising:

• glass and semiconductor layers electrostatically sealed together;
• a capacitor plate;
• a deflectable diaphragm formed in said semiconductor layer;
• a conductive sealing grid to which a voltage is applied for achieving said electrostatic seal;
• and
• a conductive grid for connecting said capacitor plate to said semiconductor material during an electrostatic sealing process.

A method for electrostatically sealing material layers together, comprising the steps of:

• forming a plurality of device structures on at least one of the material layers;
• sandwiching together the material layers to be electrostatically sealed;
• and
• concentrating an electric field with respect to each said device structure such that ion movement within at least one of the layers is confined to each device structure.

A multilayer transducer structure, comprising:

• a top glass substrate;
• a bottom glass substrate;
• a semiconductor wafer sandwiched between said top and bottom glass substrates, said semiconductor wafer including a clamped diaphragm spaced apart from said top and bottom glass substrates to define respective capacitor gaps, said semiconductor wafer further including a contact on an upper surface thereof for providing electrical connections to said semiconductor wafer;
• said top glass substrate including a top capacitor plate formed on an under surface thereof, and a hole therein, and a conductor path connected to said top capacitor plate, routed through said hole and to a top side of said top glass substrate;
• and
• said bottom glass substrate including a hole therein for communicating fluid pressure to said diaphragm, and a conductive bottom capacitor plate formed on a top surface of said bottom glass substrate connected by a conductor path through said hole to an undersurface of said bottom glass substrate, to an edge thereof and around said edge to a top surface of said bottom glass substrate.

A method for fabricating a three layer transducer structure, comprising the steps of:

• forming a diaphragm in a material which is at least semiconductive;
• sandwiching said diaphragm material between a top insulator and a bottom insulator;
• forming a pair of capacitor plates on respective surfaces of said top insulator and said bottom insulator so as to be adjacent said diaphragm;
• forming holes in said top and bottom insulators wafers for allowing a fluid pressure to deflect said diaphragm;
• forming a top side contact on said top insulator and electrically connected to one said capacitor plate;
• forming a top side contact to said diaphragm material and forming a cutout in said top insulator wafer for allowing access to said top side diaphragm material contact;
• and
• forming a top side contact on said bottom insulator wafer in electrical contact with the other said capacitor plate, and forming cutouts in said top insulator and said diaphragm material for allowing access to said top side contact of said bottom insulator.

A multilayer transducer, comprising:

• a top insulator substrate;
• a bottom insulator substrate;
• an intermediate wafer sandwiched between said top and bottom substrates, said intermediate wafer including a diaphragm spaced apart by gaps from said top and bottom glass substrates;
• a conductive top capacitor plate formed on an under surface of said top substrate;
• a conductive bottom capacitor plate formed on a top surface of said bottom glass substrate,
• a contact formed on a top side of said bottom insulator substrate electrically connected to said bottom capacitor plate;
• a contact formed on a top surface of said intermediate wafer;
• a cutout in said intermediate wafer providing access to said top side contact on said bottom insulator substrate;
• a first cutout in said top insulator substrate providing access to said bottom capacitor plate contact;
• and
• a second cutout in said top insulator substrate providing access to said intermediate wafer contact.

A method for fabricating a multilayer transducer having a semiconductor diaphragm, comprising the steps of:

• forming a diaphragm in a semiconductor layer;
• forming a capacitor plate on an upper and lower insulator substrate;
• sandwiching said semiconductor layer between said upper and lower insulator substrates so that said diaphragm is spaced apart from said capacitor plates;
• forming electrical contacts to said capacitor plates and to said semiconductor layer;
• and
• forming a second electrical contact to said semiconductor layer for allowing electrical measurements of said semiconductor material to determine parameters thereof.

In a trilevel transducer structure, a quadrature unit cell, comprising:

• a top insulator substrate having quadrants defining four die, said quadrants having four corners, each with a large hole formed therein and an intermediate size hole located between each said large hole, and a small size hole substantially centered in each said die, a conductive land area connected by a path through each said small hole to a conductive capacitor plate, each said land area being connected together by a conductive path to a conductive pad centered in each quadrant;
• a bottom insulator substrate having quadrants defining four die, said quadrants having four corners, each with a first conductive via connected to a second conductive via which is substantially centered in each said die, said centered via being connected to a conductive capacitor plate;
• and
• a semiconductor wafer sandwiched between said top and bottom insulator substrates, said semiconductor wafer having a quadrant defining four die, said wafer quadrants having four corners each with a hole, and each wafer quadrant having a diaphragm substantially centered in each said die, and an electrical contact connected to the semiconductor material of each said die.

A method for fabricating a multilayer transducer, comprising the steps of:

• fabricating a plurality of transducer structures as a multilayered composite, each said transducer structure sharing at least a portion of an edge thereof with other transducer structures;
• forming a conductive via in one or more of said layers;
• and
• sectioning said multilayered structure along said edge and through said conductive via into a plurality of individual transducer devices such that each said device includes a conductive path from a bottom surface to a top surface thereof and around an edge.

A method for fabricating a support substrate adapted for use in constructing transducers, comprising the steps of:

• forming a plurality of small holes in a spaced apart manner through a support substrate material, each said hole defining an aperture for communicating a fluid pressure therethrough;
• forming a plurality of conductive capacitor plates associated with each said small hole;
• forming a plurality of conductive areas on an opposing side of said support substrate material, and each conductive area being associated with a respective said capacitor plate;
• connecting said conductive areas with respective said capacitor plates by a conductive via through said small holes;
• and
• forming conductive paths from said conductive areas for providing an electrical connection to said capacitor plates.

A transducer structure, comprising:

• a top and bottom glass substrate characterized by a composition of weight of about:
• 80.4% SiO.sub.2
• 13.0% B.sub.2 O.sub.3
• 2.0% AL.sub.2 O.sub.3
• 3.8% Na.sub.2 O.sub.3
• 0.5% Sb.sub.2 O.sub.3
• 0.25% As.sub.2 O.sub.3
• a plurality of capacitor plates;
• a semiconductor wafer with a plurality of diaphragms formed therein;
• said semiconductor wafer being electrostatically sealed between said top and bottom glass substrates so that each said diaphragm is spaced apart from said capacitor plate;
• and
• conductors providing electrical connections to said capacitor plates and said diaphragms.

A method for fabricating a composite transducer structure, comprising the steps of:

• fabricating a first and second glass layer, each having a plurality of conductive capacitor plates;
• fabricating a semiconductor wafer having a plurality of thin diaphragm areas;
• registering the capacitor plates of one said glass layer to the diaphragms of said semiconductor wafer and adhering the layers together;
• registering the capacitor plates of the other glass layer to the diaphragms of said semiconductor wafer and adhering the layers together;
• and
• electrostatically sealing the glass layers to the semiconductor wafer to thereby form a composite transducer structure.

A miniature pressure transducer, comprising:

• a top insulator having a conductive capacitor plate formed on an under surface thereof;
• a bottom insulator having a conductive capacitor plate formed on a top surface thereof;
• a semiconductor material sandwiched between said top and bottom insulators, a surface contact providing electrical connections to said semiconductor material, said semiconductor material including a thin diaphragm formed centrally therein and spaced apart from the respective capacitor plates of said top and bottom insulators;
• said top and bottom insulators and said semiconductor material having length and width dimensions less than about 500 mils;
• and
• conductive paths formed on a top surface of said top insulator and on a bottom surface of said bottom insulator for providing connections to said capacitor plates of said top and bottom insulators.

A method for forming an electrical surface contact on an internal surface of a multilayer composite, comprising the steps of:

• forming a hole in one layer of said multilayer composite to expose a portion of said internal surface;
• covering said one layer with an apertured stencil plate and registering said aperture with respect to said hole in said one layer;
• depositing a conductive material over a surface of said stencil plate such that the conductive material passes through said aperture and through said hole and is deposited on said internal surface without filling said hole with the conductive material;
• and
• removing the stencil plate from the multilayer composite.

A method for fabricating a multilayered transducer structure, comprising the steps of:

• fixing together an insulator layer having holes therein and having a plurality of fixed capacitor plates, with a semiconductor layer having a corresponding plurality of deflectable diaphragms;
• covering said insulator layer with an apertured stencil plate, said apertures being registered with said holes in said insulator layer;
• and
• depositing a conductive material through said insulator layer holes and through said stencil plate apertures and onto said semiconductor layer to form electrical conductors.

A method of etching a semiconductor wafer, comprising the steps:

• patterning the wafer to define areas of exposed semiconductor material to be etched;
• removing semiconductor surface oxides by applying an alkaline etchant to the exposed semiconductor areas to provide exposed areas of virgin semiconductor material;
• and
• before the developing of further surface oxides on the exposed areas of the semiconductor material, etching the exposed virgin semiconductor areas with a quaternary ammonium hydroxide etchant to achieve a smooth semiconductor surface.

A method for forming holes in a semiconductor wafer, comprising the steps of:

• masking and patterning the semiconductor wafer to define areas for forming the holes therein, said patterning including removing the mask material in a path around each semiconductor area to be removed;
• etching the wafer to remove the semiconductor material in the paths so as to form a thinned area circumscribing each central part which is not thinned;
• and
• applying a pressure to each central unthinned area so as to fracture the thinned semiconductor material and allow the central parts to be removed.