Memory cell and read circuit

A read circuit for a memory array, comprising:

• at least one storage unit for storing at least one data signal;
• at lease one pass device and at least one pass/isolation device associated with each storage unit, the pass device and the pass/isolation device each having a signal path and a control terminal;
• each storage unit being coupled to the control terminal of its associated pass/isolation device, the signal path of the pass/isolation device being coupled at one end to a common control line and coupled at the other end to one end of the signal path of the pass device, the other end of the pass device signal path being coupled to a common read line, the control terminal of the pass device being coupled to an enable line;
• and
• a common driver having a signal path coupled between the common read line and a common constant-signal node, and having a control terminal coupled to the common control line, and arranged to cause a read signal proportional to the data signal stored in any one storage unit to appear on the common read line in response to an enable signal on the enable line associated with that storage unit.

A memory cell comprising:

• a storage unit for storing a data signal;
• a pass device and a pass/isolation device, each having a signal path and a control terminal, the signal paths therethrough being coupled together in series between a control node and a first constant-signal node, the control terminal of the pass device being coupled to an enable line and the control terminal of the pass/isolation device being coupled to the storage unit;
• and
• a driver having a signal path coupled between the read line and the first constant-signal node, and having a control terminal coupled to the control node, and arranged to cause a read signal proportional to the data signal to appear on the read in response to an enable signal on the enable line.

A single-bit dual-port BICMOS static RAM memory cell comprising:

• write word line and read word line;
• a write bit line and read bit line;
• a single-bit flip- storage unit comprising two cross-coupled inverters, the first inverter comprising first and field-effect transistors of opposite types, the source-drain current path of the first FET being coupled between a voltage source and a first internal node the source-drain current path of the second FET b coupled between the first internal node and ground the gate terminals of the first and second FET coupled together and to a second internal node;
• the second inverter comprising third and fourth FETs of opposite types, the source-drain current path of the third. FET being coupled between the voltage source and the second internal node, the source-drain current path of the fourth FET being coupled between the second internal node and ground, and the gate terminals of the third and fourth FETs being coupled together and to the first internal node;
• a write pass device comprising a fifth FET, the source-drain current path of which is coupled between the write bit line and the first internal node, and the gate of terminal which is coupled to the write word line;
• a read pass device and a read pass/isolation device comprising, respectively, sixth and seventh FETs, having their source-drain current paths coupled in series and between the read bit line and a control node, the gate of the sixth FET being coupled to the read word line and the gate terminal of the seventh FET being to the first internal node;
• an impedance comprising an eighth FET, the source-drain current path of which is coupled between the control node and ground, and the gate terminal of which is coupled to the read bit line;
• and
• a read bit line driver comprising a bipolar transistor, the collector of which is coupled to the read bit line, the emitter of which is coupled to ground and the base of which is coupled to the control node.

A data read circuit for column of memory cells, comprising:

• a common read bit line;
• a common control line;
• a plurality of read word lines;
• a plurality of single-bit st units each storage unit having an output coupled to the gate terminal of a first yield-effect transistor (FET) associated with such storage unit, such FET comprising a pass/isolation device, the source-drain path of such FET being coupled at one end to the common control line and coupled at the other end to one end of the source-drain current path of a second FET associated with such storage unit, such FET comprising a pass device, the other end of such current path being coupled to the common read bit line, the gate of the second FET being coupled to a particular read word line;
• a bipolar transistor comprising a common bit line driver device, the collector of which is coupled to the common read bit line, the emitter of which is coupled to ground and the base of which is coupled to the common control line;
• and
• an FET comprising an impedance device, the source-drain current path of which is coupled between the common control line and ground, and the gate of which is coupled to the common read bit line.

A single-bit, dual-port, BICMOS static RAM memory cell, comprising:

• a write word line and a read word line;
• a write bit line and a read bit line;
• a single-bit flip-flop storage unit comprising two cross-coupled inverters, the first inverter comprising first and second field-effect transistors (FETs) of opposite types, the source-drain current path of the first FET being coupled between a voltage source and a first internal node, the source-drain current path of the second FET being between the first internal node and ground, the gate terminals of the first and second FETs being coupled together and to a second internal node;
• the second inverter comprising third and fourth FETs of opposite types, the source-drain current path of the third FET being coupled between the voltage source and the second internal node, the source-drain current path of the fourth FET being coupled between the second internal node and ground, and the gate terminals of the third and fourth FETs being coupled together and to the first internal node;
• a write pass device comprising a fifth FET, the source-drain current path of which is coupled between the write bit line and the first internal node, and the gate terminal of which is coupled to the write word line;
• a read pass device and a read pass/isolation device comprising, respectively, sixth and seventh FETs, having their source-drain current paths coupled in series and between the voltage and a control node, the gate terminal of the gate being coupled to the read word line and the gate terminal of the seventh FET being coupled to the second internal node;
• an impedance comprising an eighth FET, the source-drain current path of which is coupled between the control node and ground, and the gate terminal of which is coupled to the read word line;
• and
• a read bit line driver comprising a bipolar transistor, the collector of which is coupled to the voltage source, the emitter of which is coupled to the read bit line and the base of which is coupled to the control node.

A continuous-read memory cell comprising:

• a storage unit for storing a data signal;
• a pass/isolation device having a signal path and a control terminal, the control terminal being coupled to the storage unit and the signal path being coupled between a read line and a control node;
• and
• a driver having a signal path coupled between the read line and a constant-signal node, and having a control terminal coupled to the control node, and arranged to cause a read signal proportional to the data signal to appear continuously on the read line.

A continuous-read, dual-driver memory cell comprising:

• a storage unit for storing a data signal;
• a pass/isolation device having a signal path and a control terminal, the control terminal being coupled to the storage unit and the signal path being coupled between a read line and a control node;
• a first driver having a signal path coupled between the read line and a first constant-signal node, and having a control terminal coupled to the storage unit;
• and
• a second driver having a signal path coupled between the read line and a second constant-signal node, and having a control terminal coupled to the control node;
• the pass/isolation device and the drivers being arranged to cause a read signal proportional to the data signal to appear continuously on the read line.