Pipeline-type serial multiplier circuit

A pipeline-type serial multiplier circuit having a cellular structure for multiplying two synchronized streams of digital data, that is to say a stream A consisting of n bits {a.sub.n . . . a.sub.k . . . a.sub.1 } and a stream B consisting of p bits {b.sub.p . . . b.sub.k . . . b.sub.1 }, where n, k and p are integers, by forming in each cell of the structure, in the pipeline mode, the partial products of the multiplicand A and each bit of the multiplier B, after which the partial products are successively added at a clock frequency F, each cell of the order k comprising:

• an elementary one-bit adder which receives data x.sub.k, y.sub.k and carries c.sub.k, and which at a given instant outputs a result v.sub.k and a carry c.sub.ok, so that
• v.sub.k =(x.sub.k & y.sub.k & c.sub.k) modulo 2
• c.sub.ok =(x.sub.k & y.sub.k & c.sub.k)/2
• where c.sub.k is at a given instant equal to the carry c.sub.ok determined in a same cell during a previous clock period, after which the carry c.sub.ok is delayed so that c.sub.k =c.sub.ok (d),
• delay means for synchronizing the data output by two successive cells,
• means for temporary storage of a data bit and the carry c.sub.ok,
• characterized in that the multiplier circuit comprises means for delivering the exact result of the operation in first and second consecutive bit segments under control of a signal R, the first consecutive bit segment L being formed by the p bits having the lowest binary weight, the second consecutive bit segment H being formed by the n bits having the highest binary weight, the multiplier circuit having an output rate F/n, where n is an integer greater than p, which means for delivering comprise:
• respective means, disposed within each cell, for receiving a signal R.sub.k-1 from the previous cell;
• means for generating, after the temporary storage, data c.sub.1k so that:
• c.sub.1k =(x.sub.k & y.sub.k & c.sub.ok) modulo 2,
• the data c.sub.1k being delivered during the same clock period as the carry c.sub.ok,
• means for determining the partial segments L.sub.k and H.sub.k supplied by each cell of order k so that
• L.sub.k =L.sub.k-1 (d).R.sub.k-1 (d)+v.sub.k.R.sub.k-1 (d) and
• H.sub.k =v.sub.k.R.sub.k-1 (d)+c.sub.1k (d).R.sub.k-1 (d)
• where R.sub.k-1 (d) is the signal R.sub.k-1 applied to the cell k via the preceding cells, delayed by one clock period in the cell k,
• means for reintroducing the carry c.sub.k in the adder of the order k under control of the signal R.sub.k-1 (d) in accordance with
• ______________________________________ c.sub.k = c.sub.ok (d).R.sub.k-1 (d), for the p-1.sup.th cells, and c.sub.p = b.sub.p.R.sub.p-1 (d) + R.sub.p-1 (d).c.sub.op (d), for the pth cell, ______________________________________
• means for delaying the data c.sub.1k by a clock period in the k.sup.th cell to form c.sub.1k (d), and
• means for combining the data A and B so that all cells but the p.sup.th cell perform operations of type A.b.sub.k and the p.sup.th cell performs an operation of the type A.b.sub.p,
• the symbols used being (.):
• AND-logic;
• (+) OR-logic;
• (&):
• addition.