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US 4,992,388 AGranted
Short channel IGFET process
AssigneeMotorola, Inc.
InventorJames R. Pfiester
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AssigneeMotorola, Inc.
InventorJames R. Pfiester
Estimating the term…
A process is disclosed for the fabrication of semiconductor devices which yields a device having a very short effective channel length and having polycrystalline source and drain electrodes. In accordance with the disclosed process, a semiconductor substrate is provided having a masking element positioned on the substrate surface. A layer of polycrystalline silicon is deposited on the exposed areas of the substrate surface by the process of selective deposition. The selectively deposited polycrystalline silicon is doped with conductivity determining impurities and that impurity material is thereafter redistributed to dope the underlying substrate to form source and drain regions. The masking element is removed to expose the portion of the semiconductor surface between the source and drain regions and to allow for a subsequent optional channel implantation. A gate insulator is formed overlying that portion between the source and drain regions and a second layer of silicon is deposited to overlay the gate insulator. The second layer of silicon is patterned to form the gate electrode of the insulated gate field effect transistor.
A process for the fabrication of a semiconductor device comprising the steps of:
A process for the fabrication of a semiconductor device comprising the steps of:
A process for the fabrication of a semiconductor device comprising the steps of:
A process for fabricating an insulated gate field effect transistor comprising the steps of:
Dependencies are inferred from the claim text.