Graphics system with graphics controller and DRAM controller
AssigneeU.S. Philips Corporation
InventorJean-Michel Callemyn
Life of this patent
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Abstract
A graphics system comprising a screen processor which separately formulates the requests for access to a single word and the requests for access to a plurality of consecutive words, a bus arbitrator to arbitrate the requests for access to a single word and to select a request, and a DRAM Dynamic Random Access Memory, controller to arbitrate the requests for a plurality of words and the refresh requests. The DRAM controller preferably comprises an automatic system which directly generates line and column control signals. The automatic system is preferably constructed in the form of a PLA (Program Logic Array).
Claims11
A graphics system comprising in combination:
- (a) A dynamic random access memory (DRAM) for storing display information words;
- (b) a control microcomputer which provides first single address memory access requests;
- (c) a graphic controller which comprises:
- (i) a microcomputer interface for coupling said graphics controller to said control microcomputer;
- (ii) a graphics processor which provides second single address memory access requests;
- (iii) a display processor which provides third single address memory access requests, first multi-address memory access requests and second multi-address memory access requests, and which comprises a synchronization generator for interfacing said graphics controller to a graphics display;
- (d) first arbitrating means for receiving said first, second and third single address memory access requests and for selecting therefrom a preselected request;
- and
- (e) a DRAM controller comprising second arbitrating means for receiving said preselected request, and said first and second multi-address memory access requests and for selecting therefrom an executable request for processing in said DRAM.
A graphics controller for use in a graphics system comprising in combination a DRAM for storing display information words, a control microcomputer which provides first single address memory access requests, a first arbitrating means, and a DRAM controller comprising second arbitrating means, said graphics controller comprising:
- (a) a microcomputer interface for coupling said graphics controller to said control microcomputer;
- (b) a graphics processor which provides second single address memory access requests;
- (c) a display processor which provides third single address memory access requests, first multi-address memory access requests and second multi-address memory access requests, and which comprises a synchronization generator for interfacing said graphics controller to a graphics display;
- wherein said first arbitrating means receives said first, second and third single address memory access requests and selects therefrom a preselected request and said second arbitrating means receives said preselected request and said first and second multi-address memory access requests and selects therefrom an executable request for processing in said DRAM.
A DRAM controller for use in a graphic system comprising in combination:
- (a) a DRAM for storing display information words;
- (b) a control microcomputer which provides first single address memory access requests;
- (c) a graphics controller which comprises:
- (i) a microcomputer interface for coupling said graphics controller to said control microcomputer;
- (ii) a graphic processor which provides second single address memory access requests;
- (iii) a display processor which provides third single address memory access requests, first multi-address memory access requests and second multi-address memory access request, and which comprises a synchronization generator for interfacing said graphics controller to a graphics display;
- and
- (d) first arbitrating means for receiving said first, second and third single address memory access requests and selecting therefrom a preselected request;
- wherein said DRAM controller comprises second arbitrating means for receiving said preselected request and said first and second multi-address memory access requests and selects therefrom an executable request for processing in said DRAM.
Dependencies are inferred from the claim text.