High speed sensor system using a level shift circuit

A random access memory for writing in and reading out of memory cells data information through corresponding data lines, disposed as pairs of complementary data lines, wherein the read-out of data information is performed by a sense amplifier arrangement coupled between a first supply potential and a second supply potential, comprising:

• a precharging switching circuit, coupled too said data lines, being in an ON state for precharging said data to a level of about said first supply potential and being in an OFF state during a read-out sense mode of operation of said memory;
• a level shift circuit having inputs respectively coupled to at least one pair of complementary data lines and having outputs for providing level shifted differential signals in accordance with a potential level shift of a value which is intermediate that of the potential difference between said first and second supply potentials;
• and
• a differential sensing circuit, coupled between said first and second supply potentials, having a pair of inputs respectively coupled to the outputs of said level shift circuit and providing an output level in accordance with the level shifted differential signals, said output level being representative of the data information stored in a selected memory cell of said semiconductor memory.

A clocked random access memory device (RAM) comprising:

• at least one memory array of a multi-bit construction that simultaneously inputs and simultaneously outputs multi-bit storage data through a plurality of inputs and outputs, wherein each memory array of said at least one memory array is comprised of a plurality of word lines, a plurality of pairs of complementary data lines and a plurality of memory cells, each memory cell thereof being coupled with a corresponding word line and a corresponding pair of complementary data lines thereby forming a matrix arrangement of rows and columns of memory cells, said plurality of pairs of complementary data lines thereof being disposed as individual subgroups of complementary data line pairs;
• a precharging switching circuit, coupled to each subgroup of complementary data line pairs, being in an ON state for precharging said plurality of pairs of complementary data lines to a level of about a first supply potential and being in an OFF state during a read-out operation mode of said RAM;
• a plurality of column switches, wherein each one of said subgroups is controllably coupled through a corresponding column switch to a corresponding pair of writing complementary common data lines during a write operation mode and to a corresponding pair of reading complementary common data lines during said read-out operation mode;
• wherein each writing and reading complementary common data line pairs are respectively coupled to a corresponding one of said plurality of inputs and outputs through a corresponding inputting and writing amplifier circuit and a corresponding sensing amplifier and output circuit, respectively;
• wherein during each occurrence of said read-out and writing operation modes each column switch selectively accesses a pair of complementary data lines to a corresponding reading complementary common data line pair and to a corresponding writing, complementary common data line pair, respectively, in accordance with receiving a corresponding column address;
• and
• wherein each said sensing amplifier, coupled between first and second supply potentials, is comprised of a level shift circuit having inputs coupled to a corresponding pair of reading, complementary common data lines and having outputs for providing level shifted complementary signals, during said read-out operation mode, said inputs being initially precharged prior to said read-out operation mode to a potential level corresponding to the precharge level of said complementary data lines which is effected prior to a read-out mode, and a differential sensing circuit having a pair of inputs respectively coupled to the outputs of said level shift circuit and providing complementary outputs in accordance with said level shifted complementary signals, wherein said level shifted complementary signals have a potential difference therebetween such that an intermediate level thereof is of about half the difference between said first and second supply potentials.

A clocked two-port random access memory (2-port RAM) device comprising:

• a memory array wherein there is effecting writing-in and reading-out data of a selected memory cell thereof through a respective input and output of said device independently and asynchronously, and wherein said memory array is comprised of an X-Y arrangement of word lines and pairs of complementary bit lines, and a plurality of memory cells, each memory cell being coupled with a corresponding word line and a corresponding complementary bit line thereby forming an X-Y matrix arrangement of memory cells;
• bit line writing selector means for selecting a pair of complementary bit lines in response to a corresponding Y-address writing signal for writing input data in a memory cell accessed by a corresponding word line signal in accordance with an X-address writing signal;
• bit line reading selector means for selecting a pair of complementary bit lines in response to a corresponding Y-address reading signal for reading out data from a memory cell accessed by a corresponding word line signal in accordance with an X-address reading signal;
• reading and writing complementary common data line pairs being coupled to a data read-out terminal through a sensing amplifier and output circuit and to data write-in terminal through a data writing circuit, respectively;
• wherein during implementation of a reading and writing operation said data line reading selector means accesses a pair of complementary bit lines to said reading complementary common data line pair and said data line writing selector means accesses a pair of complementary bit lines to said writing complementary common data line pair, respectively, in accordance with corresponding reading and writing Y-address signals when the RAM is enabled;
• and
• wherein said sensing amplifier, coupled between first and second supply potential, is comprised of a level shift circuit having inputs coupled to a corresponding pair of reading, complementary common data lines and having outputs for providing level shifted complementary signals, during a read-out operation mode, said inputs being initially precharged prior to said read-out operation mode to a potential level of about said first supply potential corresponding to a precharge level of said complementary bit lines which is effected prior to a read-out mode, wherein precharging of said complementary bit lines prior to said read-out mode is effected by a precharging switching circuit, coupled to said complementary bit lines, being in an ON state during a precharging period and being in an OFF state during said read-out operation mode, and a differential sensing circuit having a pair of inputs respectively coupled to the outputs of said level shift circuit and providing complementary outputs in accordance with said level shifted complementary signals, said level shifted complementary signals have a potential difference therebetween with an intermediate level of about half the difference between said first and second supply potentials.