Subsampling time-domain digital filter using sparsely clocked output latch

A combination comprising:

• a plurality of clocked bit latches N in number identified by respective ones of consecutive ordinal numbers zeroeth through (N-1).sup.th, N being a positive integer at least two said zeroeth through (N-1).sup.th clocked bit latches sharing with each other
• a single means for generating a first succession of pulses at a given pulse rate, said zeroeth through (N-1).sup.th clocked bit latches sharing with each other
• single means for generating a second succession of pulses at a submultiple of said given pulse rate, and said zero through (N-1).sup.th clocked bit latches each having
• respective initial and final clocked logic inverters, one of said respective initial and final clocked logic inverters being clocked by said first succession of pulses and the other being clocked by said second succession of pulses, said respective initial and final clocked logic inverters each having a respective input connection and having a respective output connection with associated capacitance, the input connection of said respective initial clocked logic inverter providing an input connection for said further clocked bit latch, the output connection of said respective initial clocked logic inverter connecting to the input connection of said respective final clocked logic inverter, and the output connection of said respective final clocked logic inverter providing an output connection for said further clocked bit latch;
• and
• a plurality of multiplexers, N in number, identified by respective ones of consecutive ordinal numbers zeroeth through (N-1).sup.th, each said multiplexer having an output connection to the input connection of said clocked bit latch identified by the same ordinal number, each said multiplexer having a first input connection and a second input connection selectively connected to its output connection responsive to a control signal, each of said multiplexers except the (N-1).sup.th having its first input connection connecting from the output connection of the clocked bit latch identified by an ordinal number one larger than the ordinal number it is identified by;
• means for supplying respective bits of a plural-bit input signal to the second input connections of said multiplexers;
• and
• means for taking serial bits of an output signal from the output connection of said zeroeth clocked bit latch at said submultiple of said given pulse rate.

In combination:

• means for supplying plural-phase non-overlapping clock signals comprising first and second trains of pulses occurring at a given pulse rate, successive pulses of which first and second pulse trains alternate in occurrence, said first and second trains of pulses corresponding respectively to a first phase and to a second phase of said non-overlapping clock signals;
• means receptive of said plural-phase non-overlapping clock signals for supplying N-parallel-bit subsampler input signal samples at said given pulse rate, N being a positive plural integer;
• and
• a subsampler for serially generating subsampler output signal samples each having N bits that correspond to the N bits in each (2.sup.N).sup.th successive one of said N-parallel-bit subsampler input signal samples, said subsampler comprising:
• a respective multiplexer corresponding to each of the N different bits of a subsampler input signal sample, having a first input connection for receiving that bit, having a second input connection, having a control connection, and having an output connection, said multiplexers being identified by consecutive ordinal numbers beginning with zeroeth and ending with (N-31 1).sup.th ;
• respective first and second clocked logic inverters connected in a cascade connection from the output connection of each said multiplexer to provide a respective clocked bit latch, said cascade connection from the output connection of the zeroeth multiplexer being for supplying said subsampler output signal samples, and each other cascade connection from the output connection of one of said multiplexers being connected to the second input connection of the multiplexer identified by next lower ordinal number than it is, each of said first and second clocked logic inverters having a respective clock port and a respective output capacitance, said first and second clocked logic inverters in each cascade connection being connected in a same prescribed order, either first before second or first after second;
• means for applying, to the clock ports of said first clocked logic inverters, responses to only each (2.sup.N /N).sup.th ones of the pulses in said first train;
• means for applying the pulses in said second train to the clock ports of said second clocked logic inverters;
• and
• means for applying control signals to the control connections of said multiplexers that condition them to select to their respective output connections responses to the bits received at their respective input connections, said selection being made only each N.sup.th time the clocked bit latch connecting directly from said multiplexer output connection receives a (2.sup.N /N).sup.th one of the pulses in one of said first and second trains.

In combination:

• means for supplying plural-phase non-overlapping clock signals comprising first and second trains of pulses occurring at a given pulse rate, successive pulses of which first and second pulse trains alternate in occurrence, said first and second trains of pulses corresponding respectively to a first phase and to a second phase of said non-overlapping clock signals;
• means receptive of said plural-phase non-overlapping clock signals for supplying N-parallel-bit subsampler input signal samples at said given pulse rate, N being a positive plural integer;
• and
• a subsampler for generating output signal samples that replicate each Nth one of said subsampler input signal samples, said subsampler having for each bit place of its said subsampler input signal samples:
• respective first and second clocked logic inverters connected in cascade connection to provide a respective clocked bit latch for generating a respective bit place of the output signal samples of said subsampler, said respective first and second clocked logic inverters each having a respective clock port and a respective output capacitance, said first and second clocked logic inverters in each cascade connection being connected in a same prescribed order, either first before second, or first after second;
• means for applying to the clock ports of said first clocked logic inverters responses to only each (2.sup.N).sup.th ones of the pulses in said first train;
• and
• means for applying the pulses in said second train to the clock ports of said second clocked logic inverters.

In combination:

• first, second, third and fourth clocked logic inverters each having a respective input connection, a respective output connection with associated capacitance and respective ports for receiving a respective clocking signal thereto, the output connection of said first clocked logic inverter connecting to the input connection of said second clocked logic inverter, the output connection of said second clocked logic inverter connecting to the input connection of said third clocked logic inverter, the output connection of said third clocked logic inverter connecting to the input connection of said fourth clocked logic inverter;
• means for generating a clock signal having first and second phases of non-overlapping pulses respectively serving as clocking signals for said first clocked logic inverter and for said second clocked logic inverter;
• first pulse-applying means, receptive of the pulses in said first phase of said clock signal, for applying at least some of them as clocking signals to said third clocked logic inverter;
• second pulse-applying means, receptive of the pulses in said second phase of said clock signal, for applying at least some of them as clocking signals to said fourth clocked logic inverter;
• and
• blanking means included in one of said first and second pulse-applying means so that one of said first and second pulse-applying means applies, as said clocking signal therefrom, only every Nth pulse it is receptive of, N being a positive plural integer.