US 4,978,639 AGranted

Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips

AssigneeAvantek, Inc.

InventorsChang-Hwang Hua, Simon S. Chan, Ding-Yuan S. Day, Adrian C. Lee

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Abstract

Metallized via-holes and a wraparound metal plating are simultaneously formed on semiconductor chips by patterning a photoresist mask on the front surface of the wafer to open windows over metal pads as well as the grid areas where wraparound plating is desired; etching off the exposed metal if necessary and forming via-holes and grooves in the wafer by reactive ion etching to a depth which is less than the total thickness of the wafer; depositing a thin conductive film along the walls of the grooves and via-holes by electroless methods; plating the walls of the grooves and the via-holes with conductive metal by electrolytic methods; removing the back surface of the wafer ("backlapping") along with the floors of both the grooves and the via-holes, to expose the metal on the wall of the via-holes and separate the individual chips; and, depositing conductive metal on the back surface of the individual chips to complete the grounding path.

Claims8

Dependent claims

A method for simultaneously producing plated via-holes and wraparound plating in semiconductor chips formed from a semiconductor wafer having a front surface including a plurality of metal pads, a back surface, and a thickness measured from the front surface to the back surface, the method comprising the steps of:

(i) forming via-holes and grooves in the wafer from its front surface, the grooves defining the boundaries of individual semiconductor chips, the grooves and the via-holes extending from the front surface of the wafer to a depth within the wafer which is less than the total thickness of the wafer, the via-holes being formed through selected metal pads, the grooves and via-holes each having walls and a floor;
(ii) simultaneously plating the walls and floor of the grooves and the via-holes with conductive metal;
(iii) removing a portion of the back surface of the semiconductor wafer to a depth sufficient to remove the floor of both the grooves and the via-holes, thereby exposing the metal plating located on the walls of both the via-holes and the grooves, thus separating the individual chips;
and
(iv) plating the back surface of the individual chips with conductive metal.

2 more elements

Dependencies are inferred from the claim text.