US 4,977,494 A · High speed digital motion controller architecture

Abstract

A system bus (13) carrying multidimensional path data interfaces with a plurality of local microprocessors (24), one for each dimension, through a plurality of dual access memory structures (21), one for each local microprocessor (24). A local arbiter (35) controls access to each dual access memory structure (21), facilitating elimination of wait states in data transfers between the bus (13) and memory (21) and between the local microprocessor (24) and memory (21). The arbiter (35) is implemented using a programmable logic device state machine approach, which implements a mode of operation wherein the circuitry is armed for a transfer between a local microprocessor (24) and the dual access memory (21) and accomplishes such transfer with no wait states. The state machines and dual access memory (21) are driven by a clock which is twice as fast as that driving the local microprocessor (24) and the state machine implementation utilizes this fact to insure memory access to both the system bus (13), and the local microprocessor (24) with priority going to the local microprocessor (24).

A digital architecture for a motion controller comprising:

a system bus for supplying path data, said path data including a plurality of subsets of path data, each subset corresponding to a desired trajectory of a selected dimension of motion;
a plurality of digital processor means, one for each dimension of motion, each processor means for computing a control signal for its dimension of motion utilizing the subset of path data corresponding thereto;
a plurality of memory means, each connected to said system bus and to a respective one of said plurality of digital processor means for receiving and storing the corresponding subset of said path data from said bus and for storing data transferred to and from the connected processor;
a plurality of control means, one connected to each of said memory means, for receiving control signals from said system bus and from said respective one of said plurality of digital processor means connected to the memory means, for controlling access to the connected memory means in response to said control signals;
wherein each said memory means comprises:
a random access memory means for storing said corresponding subset of path data;
a first gating buffer means responsive to a first buffer gating control signal for gating said subset of path data between said system bus and said random access memory means;
and
a second gating buffer means responsive to a second buffer gating control signal for gating said subset of path data between said respective one of said digital processor means and said random access memory means;
wherein each said control means comprises:
means responsive to a first request for access received over said system bus to generate a first access grant control signal and to a second request for access received from said respective one of said digital processor means to generate a second access grant control signal;
and
sequencer means responsive to said first access grant control signal to generate said first buffer gating control signal and to said second access grant control signal to generate said second buffer gating control signal;
wherein said means responsive to a request for access comprises a state machine means for occupying a first state and a second state, said first state being entered in response to a said second request for access, the second state being entered in response to a said first request for access;
said architecture further including a first clock means producing a succession of clock edges and wherein said state machine means runs in response to said succession of clock edges and generates said second access grant signal at a first edge of said clock;
and wherein said sequencer means enables said second gating buffer means and said random access memory means and causes completion of data transfer between said respective one of said digital processor means and said random access memory means upon occurrence of the next clock edge in said succession after said first clock edge;
said architecture further including second clock means for driving said respective one of said digital processor means, the clock rate of said first clock means being selected to be higher than that of said second clock means and such that a data transfer is achieved between said respective one of said digital processor means and said random access memory means before said digital processor means is capable of raising another said second request for access.

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High speed digital motion controller architecture

Life of this patent

High speed digital motion controller architecture

Life of this patent

Abstract

Claims20