Floating-point processor having pre-adjusted exponent bias for multiplication and division
AssigneeInternational Business Machines Corporation
InventorDonald L. Freerksen
Life of this patent
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Abstract
A floating-point arithmetic unit includes an exponent unit for biased exponents. Combinatorial bias-adjust logic removes the bias from one operand exponent before the two operand exponents are added together in adder for a multiply operation, and inserts a bias into one exponent before the exponents are subtracted by the adder for a divide operation.
Claims11
A floating-point arithmetic processor for performing multiply and divide operations upon first and second operands each having a fraction part and an exponent part, said exponent part of each operand having a bias offset, said arithmetic unit comprising:
- a multiply/divide signal for selecting one of said operations;
- a fraction unit for executing said multiply and divide operations upon said fraction parts so as to produce a fraction part of a result;
- a first exponent register for holding the exponent part of said first operand;
- a second exponent register for holding the exponent part of said second operand;
- bias-adjust means coupled to said second exponent register and responsive to said multiply/divide signal for selectively removing said bias offset from and including said bias offset in said second operand so as to produce an adjusted operand exponent;
- an exponent adder, separate from and coupled to said bias-adjust means, coupled to said first register and responsive to said multiply/divide signal, for selectively adding and subtracting said adjusted operand exponent and the exponent of said first operand so as to produce a result exponent having the same bias offset as the exponent parts of said first and second operands;
- means for storing said result exponent.
Dependencies are inferred from the claim text.