Modular digital signal processing system

A signal processor for processing a sequence of input values X.sup.(1) (m) wherein m are successive integers, comprising:

• an analyzer means having a sequence input port and a sequence output port;
• and
• a de-interleaver means having an input port and first and second output ports,
• a first de-interleaver connecting means for connecting the input port of the de-interleaver means to the output port of the analyzer means;
• and
• a second de-interleaver connecting means for connecting the first output port of the de-interleaver means to the input port of the analyzer means;
• said analyzer means comprising means, responsive to the sequence of input values X.sup.(1) (m) and sequences of input values X.sup.(i) (m) for i=2 to J, J a positive integer greater than one, wherein m are successive integers, at its input port for outputting at its output port sequences of output values Y.sup.(i) (m) for i=1 to J, given by ##EQU32## where N.sub.i for i=1 to J are even positive integers, and k, i=1 to J, k=0 to N.sub.i -1, are numerical constants which, for each i, satisfy for all even integers j the equation ##EQU33## said de-interleaver means having means, responsive to the sequence of values Y.sup.(i) (m), i=1 to J-1, at its input port, for outputting at the first output port a sequence of values X.sup.(i+1) (m) equal to Y.sup.(i) (2m) and for outputting at the second output port a sequence of values S.sup.(i) (m) equal to Y.sup.(i) (2m+1).

A signal processor for processing an ordered array of input values X.sup.(1) (m,n) wherein m and n each represent successive integers, comprising:

• an analyzer means having an array input port and first and second array output ports;
• and
• a de-interleaver means having an input port and first and second output ports,
• a first de-interleaver connecting means for connecting the input port of the de-interleaver means to the first array output port of the analyzer means;
• a second de-interleaver connecting means for connecting the first output port of the de-interleaver means to the array input port of the analyzer means;
• said analyzer means comprising means, responsive to an array of input values X.sup.(1) (m,n) at its array input port for all i=1 to J, J a positive integer greater than one, wherein m are successive integers, for outputting at its first array output port for i=1 to J-1 and at its second array output port for i=J an array of output values Y.sup.(i) (m,n) given by ##EQU40## where M.sub.i and N.sub.i, i=1 to J, are even positive integers, and .alpha..sub.j, j=0 to M.sub.i -1 and .beta..sub.k, k=0 to N-1, are numerical constants which, for each i, satisfy for all even integers s and t the equations ##EQU41## said de-interleaver means having means, responsive to the array of values Y.sup.(i) (m,n), i=1 to J-1, at its input port, for outputting at the first output port the array of values X.sup.(i+1) (m,n) equal to Y.sup.(i) (2m,2n) and for outputting at the second output port arrays of values S.sup.(i) .sub.OO (m, n), equal to Y.sup.(i) (2m+1,2n+1), (m,n) equal to Y.sup.(i) (2m+1,2n), and S.sup.(i).sub.EO (m,n) equal to Y.sup.(i) (2m,2n+1).

A single stage wavelet analyzer circuit for processing a sequence of values X(m) wherein m are successive integers, to obtain an output sequence Y(m) according to the equation ##EQU50## where N is a positive even integer, the wavelet analyzer circuit comprising:

• first and second dual-convolver circuits and an analyzer-adjunct circuit, said first dual convolver circuit comprising means for convolving the sequence of values X(m) to obtain a first sequence Y.sub.1 (m) at an output port thereof according to the equation ##EQU51## and said second dual convolver circuit comprising means for convolving the sequence of values X(m) to obtain a second sequence Y.sub.2 (m) at an output port thereof according to the equation ##EQU52## said analyzer-adjunct circuit comprising means, having input ports respectively connected to the output ports of said first and second dual convolver circuits, for processing the first and second sequences Y.sub.1 (m) and Y.sub.2 (m) to obtain the sequence Y(m) according to the relation
• Y(m)=Y.sub.1 (m-2)+Y.sub.2 (m-1) for m even
• Y(m)=-Y.sub.1 (m)+Y.sub.2 (m-1) for m odd;
• and
• the values .beta..sub.k, k=0 to N-1, are numerical constants which satisfy for all even integers j the equation ##EQU53##

A single stage wavelet synthesizer circuit for processing a sequence of values W(m) wherein m designates success integers, to obtain an output sequence Z(m) according to the equation ##EQU54## where N is a positive even integer, the circuit comprising:

• first and second dual-convolvers circuits and an analyzer-adjunct circuit, said first dual convolver comprising means for convolving the sequence of values W(m) to obtain a first sequence Z.sub.1 (m) at an output port thereof according to the equation ##EQU55## and said second dual convolver comprising means for convolving the sequence of values W(m) to obtain a second sequence Z.sub.2 (m) at an output port thereof according to the equation ##EQU56## said synthesizer-adjunct circuit comprising means, having input ports respectively connected to the output ports of said first and second dual convolver circuits, for processing the first and second sequences Z.sub.1 (m) and Z.sub.2 (m) to obtain the sequence Z(m) according to the relation
• Z(m)=Z.sub.1 (m)+Z.sub.2 (m-1) for m even
• Z(m)=-Z.sub.1 (m-2)+Z.sub.2 (m-1) for m odd
• wherein the values .beta..sub.k, k=0 to N-1 are numerical constants which satisfy for all even integers j the equation ##EQU57##

A function generator, comprising:

• a source of null sequences;
• a plurality, J in number, of successive synthesizer circuits S.sub.i, where i=1 to J, each having an input port and an output port;
• and
• J-1 interleaver circuits I.sub.i, where i=1 to J-1, each having an output port and a data input port and a null input port, for all i, i=1 to J-1, the output port of the interleaver I.sub.i is connected to the input port of the synthesizer circuit S.sub.i, the data input port of the interleaver I.sub.i is connected to the output port of the synthesizer circuit S.sub.i+1, and the null input port of the interleaver I.sub.i is connected to the output port of the processing means P.sub.i ;
• each synthesizer circuit S.sub.i comprising means, responsive to a sequence of input values W.sup.(i) (m) at its input port wherein m represents success integers, for generating and outputting at its output port a sequence of output values Z.sup.(i) (m) given by ##EQU58## each interleaver circuit I.sub.i having means for outputting at the output port the sequence of values W.sup.(i) (m), being equal to Z.sup.(i+1) (m/2) for m even and equal to T.sup.(i) ((m-1)/2) for m odd, the output port of the processing means P.sub.J being connected to input port of the synthesizer circuit S.sub.J so that the sequence W.sup.(J) (m) input to the input port of the synthesizer S.sub.J is the output sequence of the processing means P.sub.J, whereby if the effect of the processing means P.sub.i, i=1 to J is such that the sequences T.sup.(i) (m) are respectively approximately equal to the sequences S.sup.(i) (m), then the sequences Z.sup.(i) (m) are approximately equal to the respective sequences ##EQU59##