High performance sigma delta based analog modem front end

An improved low distortion four phase clocked integrator circuit for integrating an input signal, comprising:

• integrating means:
• an input signal sampling capacitor;
• a first switching means operative to connect ground to a first plate of said sampling capacitor at a first time;
• a second switching means operative to switch said input signal to a second plate of said sampling capacitor at a second time to sample said input signal;
• a third switching means operative to connect said first plate of said sampling capacitor to said integrating means at a third time;
• and
• a fourth switching means operative to connect ground to said second plate of said sampling capacitor at a fourth time;
• and
• timing means for controlling the timing of said first time, said second time, said third time, and said fourth time to control the sampling of said input signal and the transfer of charge from said sampling capacitor to said integrating means such that signal dependent charges associated with said switching means are not transferred to said integrating means.

An improved integrator circuit for integrating an input signal, comprising:

• an integrator circuit comprising an integrator input, an integrator output, and an integrating capacitor connected between said integrator output and said integrator input;
• an input signal sampling capacitor;
• first switching means for connecting said input signal to said sampling capacitor;
• second switching means for connecting said sampling capacitor to said integrator input;
• and
• timing means for controlling the times of switching by said first and said second switching means such that distortion of said input signal due to signal dependent charge injection is substantially reduced.

An improved analog-to-digital converter, comprising:

• a sigma delta modulator for converting said incoming analog signal into a bit stream of digital samples at a predetermined rate of oversampling comprising MOSFET switching means;
• a low pass digital filter responsive to said bit stream of digital samples for filtering quantization noise from said bit stream;
• a decimator connected to the output of said low pass digital filter for reducing the number of said digital samples;
• and
• means for eliminating signal-dependent charges in said MOSFET switching means of said sigma delta modulator.

A sigma delta modulator based digital to analog converter for converting an input digital signal into an analog output signal, comprising:

• oversampling means for converting said input digital signal into an oversampled digital signal;
• sigma delta modulator means responsive to said oversampled digital signal for shifting quantization noise out of the baseband of said input digital signal and for providing a one-bit pulse code modulated signal;
• one-bit digital to analog converter means for converting said one-bit pulse code modulated signal into said analog output signal;
• and
• return-to-zero means for reducing distortion in said one-bit digital to analog converter means due to unequal rise and fall times of said one-bit pulse code modulated signal.

A multistage digital filter for filtering a serial digital input signal, comprising:

• addressable memory means for storing in an interleaving fashion a plurality of filter coefficients in addressable locations for L subfilter stages, where L is an integer, and where for each of said L stages there are k subfilter coefficients, where k is an integer;
• means for retrieving said plurality of filter coefficients in a predetermined sequence during a first clock cycle;
• means for receiving said serial digital input signal at a rate corresponding to a second clock cycle, said second clock cycle being longer than said first clock cycle;
• means for forming a sum of partial products of said plurality of filter coefficients and said digital input signal for a time period corresponding to a third clock cycle, said third clock cycle corresponding to a decimation frequency;
• a plurality of L cascaded registers for storing a plurality of L accumulated partial products;
• means for summing said partial product sum with a feedback value stored in the Lth register to obtain an accumulated partial product;
• and
• means for sampling the contents of one of said L cascaded registers to provide a filtered output signal.

A digital decimating filter having L subfilter stages, where L is an integer, for filtering a serial input signal x.sub.n provided at an input rate of 1/T to provide a filtered output signal at a decimated rate 1/kT, where k is an integer, comprising:

• addressable memory means for storing a plurality N of n bit filter coefficients h in addressable locations, there being k filter coefficients for each of said L subfilter stages such that L.multidot.k=N, where n and N are integers;
• means for retrieving said plurality of filter coefficients in a predetermined sequence during a first clock cycle, said first clock cycle occurring at a frequency of L/T;
• means for receiving said serial digital input signal x.sub.n at a rate corresponding to said input rate;
• an input register for storing said digital input signal for a period of time T;
• means for retrieving the ith one h.sub.i of said k filter coefficients for each of said L subfilter stages from said memory means during said period of time T;
• multiplier means for multiplying said retrieved one h.sub.i of said filter coefficients for each of said L subfilter stages with said digital input signal x to obtain a partial product h.sub.i x.sub.n ;
• a plurality of L cascaded registers for storing a plurality of L accumulated partial products for a period of time kT;
• means for summing said partial product h.sub.i x with the value stored in the Lth register to obtain an accumulated partial product x.sub.n h.sub.i +x.sub.n -L;
• and
• output means for providing said accumulated partial product x.sub.n h.sub.i +x.sub.n -L.sup.h.sub.i -L as said filtered output signal by sampling the contents of one of said L cascaded registers at said decimation rate 1/kT.

An improved analog-to-digital converter, comprising:

• oversampling sigma delta modulator analog-to-digital converter means for converting an incoming analog signal into a plurality of digital signal samples and for shifting quantization noise out of the baseband of said incoming analog signal;
• and
• an L-stage digital finite impulse response low pass decimating filter, where L is an integer, for filtering said quantization noise from said digital signal samples, comprising:
• addressable memory means for interleavingly storing a plurality of k filter coefficients for each of said L stages in addressable locations,
• means for retrieving said plurality of filter coefficients in a predetermined sequence during a first clock cycle,
• means for receiving said digital signal samples at a rate corresponding to a second clock cycle, said second clock cycle being longer than said first clock cycle,
• means for forming a sum of partial products of said plurality of filter coefficients and said digital signal samples for a time period corresponding to a third clock cycle, said third clock cycle corresponding to a first decimation frequency,
• a plurality of L cascaded registers for storing a plurality of L accumulated partial products,
• means for summing said partial product sum with a feedback value stored in the Lth register to obtain an accumulated partial product, and
• means for sampling the contents of said accumulator means to provide a filtered output signal at said first decimation frequency.

An L-stage digital filter, where L is an integer, for filtering a serial digital input signal, comprising:

• memory means for interleavingly storing a plurality of k subfilter coefficients for each of L subfilter stages in addressable locations, where k is an integer;
• means for addressing said memory means at a clock rate of L/T, where T is the sampling period to retrieve said filter coefficients;
• means for complementing a retrieved one of said filter coefficients in response to said serial digital input signal to provide a partial product of said serial digital input signal and said retrieved filter coefficient;
• a plurality of L cascaded registers for storing a plurality of L accumulated partial products for a time period kT;
• and
• means for summing said partial product with a feedback value stored in the Lth register to obtain an accumulated partial product, and
• means for providing said accumulated partial product stored in one of said L registers as a digital output signal.