Data flow signal processor method and apparatus
AssigneeHughes Aircraft Company
InventorsThomas W. Getzinger, Hans L. Habereder, R. Loyd Harrison, Donald M. Hopp, David L. Mitchell, Chao-Kuang Pian, John A. Propster
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Abstract
A single instruction stream multiple data steam data flow signal processor and method for implementing macro data flow control, in which a plurality of data processors have contentionless access to global memory data. Data processing tasks for the data processors, such as primitive executions together with graph scheduling processes, are developed asynchronously and in parallel from a command program and a macro data flow control graph.
Claims15
A data flow signal processor architecture for implementing macro data flow control, said architecture comprising:
- a global memory having a plurality of data storage spaces and a plurality of data access ports, at least one of said data access ports providing a means for coupling data to be processed into, and processed data out of, said architecture;
- individual data processors coupled in bidirectional data transmission paths to respective ones of said data access ports;
- a graph process controller coupled to said data processors for scheduling data processing tasks defined in graphs in said individual data processors;
- command element means coupled to said graph process controller for executing a command program and for initiating graph executions in said architecture by downloading descriptions of said graphs to said graph process controller for execution thereby;
- and
- memory access controller means coupled to said graph process controller, said plurality of data processors and said global memory, for controlling access to said global memory by said data processors.
A data flow signal processor architecture for implementing macro data flow control, said architecture comprising:
- a global memory having a plurality of data storage spaces and a plurality of data access ports, at least one of said data access ports providing a means for coupling data to be processed into, and processed data out of, said architecture;
- individual data processors coupled in bidirectional data transmission paths to respective ones of said data access ports;
- a graph process controller coupled to said global memory and said data processors for defining and controlling the scheduling and execution of data processing tasks defined in graphs in said individual data processors;
- command element means coupled to said graph process controller for executing a command program and for initiating graph executions in said architecture by downloading descriptions of said graphs to said graph process controller for execution thereby;
- memory access controller means coupled to said graph process controller, said plurality of data processors and said global memory, for controlling access to said global memory by said data processors under control of the graph process controller;
- and
- external interface means coupled between the command element means, the graph process controller and the global memory for providing an interface therebetween that permits the coupling of data and control signals therebetween, and for providing a means to input and output data from the architecture.
Dependencies are inferred from the claim text.