Voltage multiplier for nonvolatile semiconductor memory

A voltage multiplier for use in nonvolatile semiconductor memory comprising:

• a plurality of basic circuits cascade-connected between a power source voltage terminal and an output terminal via a load circuit, each of said basic circuits comprising:
• a first node to which an input voltage is applied;
• a first capacitor connected at one end to said first node;
• a second node connected to the other end of said first capacitor;
• a third node to which a first clock signal is supplied;
• first level shifting means, connected between said second and third nodes and to which a power source voltage having the same amplitude as that of the first clock signal supplied to said third node is applied, for shifting the level of the first clock signal to a level higher than that of the power source voltage applied to said first level shifting means, and for outputting the first clock signal thus level-shifted to said second node;
• a first transistor which is connected at one end to said first node and whose conduction state is controlled according to the potential of said first node;
• a fourth node to which the other end of said first transistor is connected;
• a second capacitor connected at one end to said fourth node;
• a fifth node to which the other end of said second capacitor is connected;
• a sixth node to which a second clock signal, having level periods set at timings different from those of the first clock signal, is supplied;
• second level shifting means, connected between said fifth and sixth nodes and to which a power source voltage having the same amplitude as that of the second clock signal supplied to said sixth node is applied, for shifting the level of the second clock signal to a level higher than that of the power source voltage applied to said second level shifting means, and for outputting the second clock signal thus level-shifted to said fifth node;
• a second transistor which is connected at one to said fourth node and whose conduction state is controlled according to the potential of said fourth node;
• and
• a seventh node connected to the other end of said second transistor, for outputting an output voltage.