CMOS power-on reset circuit

A circuit having an output for providing an output signal in response to the power-on transient of a first power supply conductor wherein the output signal changes state at a predetermined threshold of the potential developed at the first power supply conductor independent of the slew rate thereof, comprising:

• a first transistor having a drain, a source and a gate coupled to the first power supply conductor;
• at least one diode means serially coupled between the first power supply conductor and said drain of said first transistor;
• a second transistor having a gate, a drain and a source, said gate being coupled to said drain of said first transistor, said source being coupled to a second power supply conductor, said drain being coupled to the output;
• a third transistor having a gate, a drain and a source, said gate being coupled to said second power supply conductor, said drain being coupled to said drain of said second transistor;
• a fourth transistor having a gate, a drain and a source, said drain being coupled to said source of said third transistor, said source being coupled to the first power supply conductor;
• and
• a fifth transistor having a gate, a drain and a source, said gate being coupled to the output, said drain being coupled to said source of said first transistor, said source being coupled to said second power supply conductor.

An integrated circuit having an output for providing an output signal in response to the power-on transient of a first power supply conductor wherein the output signal changes state at a predetermined threshold of the potential developed at the first power supply conductor independent of the slew rate thereof, comprising:

• a first transistor having a drain, a source and a gate coupled to the first power supply conductor;
• at least one diode means serially coupled between the first power supply conductor and said drain of said first transistor;
• a second transistor having a gate, a drain and a source, said gate being coupled to said drain of said first transistor, said source being coupled to a second power supply conductor, said drain being coupled to the output;
• a third transistor having a gate, a drain and a source, said gate being coupled to said second power supply conductor, said drain being coupled to said drain of said second transistor;
• a fourth transistor having a gate, a drain and a source, said drain being coupled to said source of said third transistor, said source being coupled to the first power supply conductor;
• and
• a fifth transistor having a gate, a drain and a source, said gate being coupled to the output, said drain being coupled to said source of said first transistor, said source being coupled to said second power supply conductor.

The method of detecting a predetermined threshold of an increasing potential supplied at a power supply conductor during power-on and providing an output signal in response thereto, comprising the steps of:

• establishing an output signal which tracks the increasing potential supplied at the power supply conductor;
• developing a control signal having a slew rate substantially equal to the slew rate of the increasing potential of the power supply conductor as the increasing potential of the power supply conductor reaches a first predetermined level;
• reducing the output signal upon detecting a predetermined level of said control signal corresponding to a second predetermined level of the increasing potential of the power supply conductor;
• and
• disabling the current flow upon detecting the reduction of the output signal.