Universal microprocessor interface circuit

An apparatus for alternatively connecting to at least one first type of microprocessor that generates first and second timing signals of a first type or to at least one second type of microprocesor that generates first and second timing signals of a second type and for producing WRITE data signals and READ data signals in response to either the first type or the second type of first and second timing signals, wherein the first and second timing signals of the first type determine whether a read operation or a write operation is to occur for the at least one first type of microprocessor and the first and second timing signals of the second type determine whether a read operation or a write operation is to occur for the at least one second microprocessor, the apparatus comprising:

• first means, responsive to the first and second timing signals of the first type, for producing the WRITE data signals and the READ data signals;
• second means, responsive to the first and second timing signals of the second type, for producing the WRITE data signals and the READ data signals;
• indicating means, responsive to the first and the second timing signals of the first type or to the first and the second timing signals of the second type, for indicating whether the first and second timing signals are of the first type or of the second type;
• and
• activating means including at least one flip-flop that can switch between a first state and a second state in response to said indicating means;
• wherein said first means produces the WRITE data signals and the READ data signals when said at least one flip-flop is in the first state;
• and
• wherein said second means produces the WRITE data signals and the READ data signals when said at least one flip-flop is in the second state.

A method for producing WRITE data signals and READ data signals in response to either first and second timing signals of a first type generated by a first type of microprocessor or in response to first and second timing signals of a second type generated by a second type of microprocessor, wherein the first and second timing signals of the first type determine whether a read operation or a write operation is to occur for the at least one first type of microprocessor and the first and second timing signals of the second type determined whether a read operation or a write operation is to occur for the at least one second mircoprocessor, the method comprising the steps of:

• providing at least one logic signal in a first logical state;
• generating an indicating signal in response to first and second timing signals of the first type or first and second timing signals of the second type;
• performing either a step of maintaining the state of the at least one logical signal in the first logical state in response to the receipt of first and second timing signals of the first type or a step of changing the state of the at least one logic signal to a second logical state in response to the receipt of first and second timing signals of the second type, according to the indicating signal;
• alternatively receiving first and second timing signals of the first type or first and second timing signals of the second type;
• producing the WRITE data signals and the READ data signals from the received signals using first means for producing when the at least one logic signal is in the first logical state;
• and
• producing the WRITE data signal and the READ data signals from received signals using second means for producing when the at least one logic signal is in the second logical state.

A method for producing WRITE data signals and READ data signals in response to either first and second timing signals of a first type generated by a first type of microprocessor or in response to first and second timing signals of a second type generated by a second type of microprocessor, wherein the first and second timing signals of the first type determine whether a read operation or a write operation is to occur for the at least one first type of microprocessor and the first and second timing signals of the second type determine whether a read operation or a write operation is to occur for the at least one second mircoprocessor, the method comprising the steps of:

• providing a flip-flop in a first logical state;
• generating an indicating signal in response to first and second timing signals of the first type or first and second timing signals to the second type;
• performing either a step of maintaining the state of the flip-flop in the first logical state in response to the receipt of first and second timing signals of the first type or a step of changing the state of the flip-flop to a second logical state in response to the receipt of initial first and second timing signals of the second type, according to the indicating signal;
• alternatively receiving first and second timing signals of the first type or first and second timing signals of the second type;
• producing the WRITE data signals and the READ data signals from the received signals using first means for producing when the flip-flop is in the first logical state;
• and
• producing the WRITE date signals and the READ data signals from the received signals using second means for producing when the flip-flop is in the second logical state.