Linear feedback shift registers for data scrambling

A linear feedback shift register for operation in accordance with a generating polynomial of order n corresponding to an n by n transition matrix T, the shift register comprising:

• k storage cells, where k and n are integers and k>n;
• means for supplying a clock signal simultaneously to all of the storage cells;
• means for deriving a k-bit word from outputs of the storage cells;
• and
• linear feedback means coupling inputs of the storage cells to respective outputs of the storage cells in accordance with a k by k transition matrix T', each row and column of the transition matrix T' corresponding to a storage cell, binary 1's in each row of the transition matrix T' indicating that that row's storage cell's input is responsive to a storage cell's output as represented by the column in which the binary 1's appear;
• where the matrix T' is the k-th power of a k by k matrix T" consisting of the n by n matrix T extended by an additional k-n rows and columns, with each of the additional rows n+1 to k representing a further connection of an input of a respective storage cell to the output of the storage cell corresponding to the preceding row of the matrix.