High resolution, fully differential CMOS comparator

A fully differential CMOS comparator utilizing a single, high-gain, fully differential, operational amplifier having a "folded cascode" configuration and having two input terminals IN+ and IN-, connected respectively to a switched capacitance input circuit for storage-subtraction of an offset voltage of the amplifier and of comparison, and two output terminals OUT+ and OUT- , functionally connected respectively to two input terminals of a latch circuit, said comparator producing on an output terminal of said latch circuit a logic signal indicative of the level of a signal fed to a first input terminal of said switched capacitance input circuit as compared to a constant reference voltage fed to a second input terminal of said switched capacitance input circuit and wherein

• said latch circuit is provided with a differential input stage formed by a differential pair of transistors having their respective sources connected in common and to the drain of a third transistor acting as a biasing current generator of the circuit;
• said differential input stage transferring an output signal produced by said high-gain, fully differential, operational amplifier to two input nodes of a latch formed by at least a pair of cross-coupled transistors and by a reset switch connected between the gates of said cross-coupled pair of transistors;
• a pair of output transistors of said fully differential, "folded cascode", operational amplifier having their respective gates connected in common and to the node of said sources connected in common of said differential pair of transistors of said differential input stage of the latch circuit, realizing a common mode feedback by means of said differential input stage of the latch circuit which controls the output common mode voltage of said high-gain operational amplifier.