Gate turn-off thyristor with switching control field effect transistor

A gate turn-off thyristor comprising:

• (a) a first emitter layer of a first type conductivity;
• (b) a first base layer of a second type conductivity electrically connected said first emitter layer and having a surface and first and second directions perpendicular to each other on the surface;
• (c) two neighboring second base layers of the first type conductivity formed in the surface of said first base layer with a predetermined interval so as to be elongated along said first direction;
• (d) second emitter layers of the second type conductivity each formed in each of said second base layers;
• (e) a gate electrode insulatively provided above a portion of said second base layer sandwiched between said second emitter layer and said first base layer and having an elongated planar shape extending along said first direction so as to be substantially self-aligned with said second base layers, said gate electrode defining a field effect transistor structure in a section along said second direction which is perpendicular to an extending direction of said gate electrode;
• and
• (f) a control electrode insulatively provided above said gate electrode to have a planar shape elongated along said first direction, said control electrode having,
• a wiring electrode extending perpendicularly to said control electrode on a plane and formed to extend downward from both sides of said gate electrode to be in contact with certain surface regions of said two neighboring second base layers at certain surface regions of said second base layers, thereby defining a gate turn-off thyristor along said first direction which is parallel to the extending direction of said gate electrode.

A MOS assisted gate turn-off thyristor comprising:

• (a) a first emitter layer of a first type conductivity;
• (b) a first base layer of a second type conductivity electrically connected to said first emitter layer and having a surface;
• (c) second base layers of the first type conductivity elongated in the surface of said first base layer with a predetermined interval;
• (d) second emitter layers of the second type conductivity formed in said second base layers;
• (e) gate electrodes insulatively provided above said second base layers and each having an elongated planar shape;
• and
• (f) a control electrode having,
• first conductive layer portions insulatively stacked above said gate electrodes to have elongated planar shapes, and
• second conductive layer portions, extending perpendicularly to said first conductive layer portions on a plane, for connecting said first conductive layer portions with said second base layers at certain surface regions of said second base layers, said first and second conductive layer portions defining a mesh-like planar pattern.