Low impedance buffer circuit
AssigneeAT&T Bell Laboratories
InventorJohn M. Khoury
Life of this patent
Estimating the term…
Abstract
A low impedance class AB buffer stage in complementary transistor technology has its quiescient current stabilized and its operation thereby made more reliable by means of suitable error op-amps that are supplied with transistor feedback loops which are connected to the stage's output terminal through resistors. In addition, for full rail-to-rail output voltage capability, transistor switching devices are added to turn off current through either of the resistors when the output voltage approaches the voltage of either power rail, and also a pair of serially rail-to-rail connected transistor is connected in parallel with the feedback loops.
Claims13
Amplifier circuitry including a buffer stage which comprises
- (a) first and second operational amplifiers each having an output terminal and a first and a second input terminal;
- (b) first and second resistance means;
- (c) first and second transistor devices respectively having first and second relatively high current carrying controlled paths and respectively having first and second relatively low current carrying control terminals;
- (d) first and second power rails;
- (e) first connection means for connecting, from the first power rail to the second power rail, serially the first high current path of the first transistor device, the first resistance means, the second resistance means, and the second high current path of the second transistor device;
- (f) second connection means for connecting a first node located between the first transistor device and the first resistance means to the second input terminal of the first operational amplifier;
- (g) third connection means for connecting a second node located between the second transistor device and the second resistance means to the second input terminal of the second operational amplifier;
- and
- (h) fourth and fifth connection means for connecting respectively the output terminal of the first operational amplifier and of the second operational amplifier to the control terminal of the first transistor device and of the second transistor device, respectively.
Dependencies are inferred from the claim text.