Sidewall capacitor DRAM cell

A dynamic RAM cell comprising:

• an MOS transfer transistor formed in a semiconductor substrate and having a source region, a drain region, a channel region, and an insulated gate, said transfer transistor being used for selectively writing data into and reading data out of said RAM cell;
• a storage capacitor comprising:
• a first electrode formed of a first electrode conductive layer positioned substantially above said semiconductor substrate and partially overlying said transfer transistor, and having a top surface and having sidewalls which are substantially vertical, said first electrode being connected through a buried contact opening to said source region;
• a second conductive electrode overlying the top surface and said sidewalls of said first conductive electrode;
• and
• a storage dielectric insulating layer located between said first and second electrodes;
• a bit line connected to said drain;
• a word line connected to said gate;
• means for connecting said channel to a fixed potential
• wherein the total area of said vertical sidewalls exceeds the area of said top surface, thereby substantially increasing the capacitances of said storage capacitor without substantially increasing the surface area taken up by said cell in said semiconductor substrate.

A dynamic multiport RAM cell comprising:

• at least two transfer MOS transistors formed in a semiconductor substrate each having a source region, a drain region, a channel region and an insulated gate, each of said transfer transistors being used as an independent port to write data into and read data out of said multiport RAM cell;
• a storage capacitor comprising:
• a first conductive layer formed above the top surface of said semiconductor substrate, and serving as a first electrode of said capacitor, said first conductive layer having a top surface;
• a trench formed into said first layer, said trench having substantially vertical sidewalls;
• a layer of storage dielectric formed on said sidewalls of said trench and on at least a portion of said top surface of said first conductive layer;
• a second conductive layer formed on said layer of dielectric and serving as a second electrode of said capacitor;
• and
• a buried contact opening allowing contact between said first or second conductive layer and each of said source regions;
• a plurality of independent word lines, each said word line connected to the gate of an associated one of said transfer transistors;
• a plurality of independent word lines, each said bit line connected to the drain of an associated on of said transfer transistors;
• means for connecting said channel region to a fixed substrate potential;
• and
• means for connecting said second electrode to a fixed plate potential;
• wherein the total area of said vertical sidewalls exceeds the area of said top surface, thereby substantially increasing the capacitance of said storage capacitor without substantially increasing the surface area taken up by said cell in said semiconductor substrate, said increased capacitance permitting the reading of the stored state simultaneously from more than one port without destroying said stored state.