CMOS complementary self-biased differential amplifier with rail-to-rail common-mode input-voltage range

A complementary metal-oxide semiconductor (CMOS) complementary, self-biased, differential amplifier for providing rail-to-rail common-mode input-voltage range comprising;

• a first transistor having its source coupled to a positive supply rail;
• a second transistor having its source coupled to the drain of said first transistor and having its drain coupled to a biasing node;
• a third transistor having its drain coupled to said biasing node;
• a fourth transistor having its drain coupled to the source of said third transistor and its source coupled to a negative supply rail;
• said first, second, third and fourth transistors having their gates coupled to said biasing node;
• a fifth transistor having its source coupled to said positive supply rail;
• a sixth transistor having its source coupled to the drain of said fifth transistor and its drain coupled to an output node;
• a seventh transistor having its drain coupled to said output node;
• an eighth transistor having its drain coupled to the source of said seventh transistor and its source coupled to said negative supply rail;
• said fifth, sixth, seventh and eighth transistors having their gates coupled to said biasing node;
• a ninth transistor having is source coupled to said positive supply rail and its drain coupled to a first node;
• a tenth transistor having its drain coupled to a second node and its source coupled to said negative supply rail;
• said ninth and tenth transistors also having their gates coupled to said biasing node;
• an eleventh transistor having it source coupled to said first node and its drain coupled to the junction of said third and fourth transistors;
• a twelfth transistor having its source coupled to said second node and its drain coupled to the junction of said first and second transistors;
• said eleventh and twelfth transistors having their gates coupled to receive a first differential input signal;
• a thirteenth transistor having its source coupled to said first node and its drain coupled to the junction of said seventh and eighth transistors;
• a fourteenth transistor having its source coupled to said second node and its drain coupled to the junction of said fifth and sixth transistors;
• said thirteenth and fourteenth transistors having their gates coupled to receive a second differential input signal;
• said first, second, fifth, sixth, ninth, eleventh and thirteenth transistors being of p-type devices;
• said third, fourth, seventh, eighth, tenth, twelfth and fourteenth transistors being of n-type devices;
• wherein a negative feedback from said biasing node provides for low sensitivity to temperature, process, supply-voltage, common-mode input-voltage variations and further provides for improved common-mode rejection while providing differential-mode amplification.