Method of packaging and powering integrated circuit chips and the chip assembly formed thereby

An IC chip assembly comprising

• a chip having an array of exposed contacts at the periphery of a first face thereof and additional chip contacts exposed at said chip first face;
• a substrate having an array of exposed contacts at a face thereof and additional substrate contacts at said substrate face;
• interposer means positioned between said chip and substrate, said interposer means including electrically insulating compliant means for providing compliance between said chip and said substrate, said compliant means having first and second opposite surfaces which face said chip and substrate respectively, first exposed contacts at said first surface of the compliant means which engage the said additional contacts of the chip, and second exposed contacts at said second surface of the compliant means which engage said additional contacts of the substrate;
• connecting means electrically connecting said first and second contacts;
• a flexible circuit lead frame mechanically and electrically attached at a first electrical end thereof to said array of chip contacts, and at a second electrical end thereof to said array of substrate contacts;
• and
• means for engaging said chip, interposer means and substrate together so that said interposer means provides compliance between said chip and said substrate and establishes relatively low inductance electrical connections between said additional contacts of said chip and said substrate.

An IC chip assembly comprising

• a chip having an array of exposed contacts at the periphery of a first face thereof and additional chip contacts exposed at said chip first face;
• a substrate having an array of exposed contacts at a face thereof and additional substrate contacts exposed at said substrate face;
• interposer means located between said chip and said substrate, said interposer means including first compliant contacts engaging said additional chip contacts, second compliant contacts engaging said additional substrate contacts and conductors electrically connecting selected ones of said first and second contacts;
• a lead frame mechanically and electrically connected at a first electrical end thereof to said array of chip contacts, and at a second electrical end thereof to said array of substrate contacts;
• heat sink means engaging the face of said chip opposite said first face thereof;
• and
• means for engaging said chip, interposer means, substrate and heat sink means together so that said interposer means simultaneously provides compliance between said chip and said substrate and establishes relatively low inductance electrical connections between said additional chip and substrate contacts and good thermal contact between said chip and said heat sink means.