US 4,954,875 A · Semiconductor wafer array with electrically conductive compliant material

Abstract

A semiconductor wafer array comprising a plurality of wafers of semiconductor material. Each of the wafers is provided with cone-shaped or pyramid-shaped vias. Inserted in each of the vias is a correspondingly shaped wad of electrically conductive compliant material for forming continuous vertical electrical connections between the wafers in the stack. The base of each wad makes connection to a bonding pad on the surface of a lower wafer as well as to the electrically conductive compliant material in the lower wafer.

Drawings

Claims21

Dependent claims

A semiconductor wafer array comprising:

a plurality of wafers of semiconductors material which are stacked one on top of another, each of said plurality of wafers having
(a) a via which is in registration with a via in an adjacent wafer, said via in each of said plurality of wafers having a first end terminated by a first hole in a first surface of each of said wafers, a second end terminated by a second and relatively larger hole in a second and opposite surface of each of said wafers, and an inwardly directed wall surface in at least a portion of the wall between said first and said second ends;
(b) means for electrically insulating an exposed surface of said via in each of said plurality of wafers between said first and said second ends;
(c) an electrically conductive pad surrounding said first hole of said via in each of said plurality of wafers for making an electrical connection to electrical circuits located on said first surface of each of said plurality of wafers;
and
(d) an electrically conductive compliant material which is located in said via in each of said plurality of wafers which, when not compressed, extends outwardly beyond respective planes of said first and said second holes of said via in each of said plurality of wafers;
and
means for stacking a first one of said plurality of wafers on top of a second one of said plurality of wafers such that the compliant material which extends beyond said second hole of said via in said first one of said plurality of wafers will make an electrical contact with said electrically conductive pad surrounding said first hole of said via in said second one of said plurality of wafers and said compliant material which extends from said first hole of said via in said second one of said plurality of wafers.

5 more elements

A semiconductor wafer array comprising:

a housing having a base plate and a top wall;
a plurality of wafers of semiconductive material which are stacked one on top of another between said base plate and said top wall, one of said wafers being located adjacent to said base plate, another of said wafers being located nearest to said top wall, each of said wafers having at least one via which is in registration with a via in another of said wafers, said via in each wafer having a first end terminated by a first hole in a first surface of said wafer, a second end terminated by a second hole in a second and opposite surface of said water, said second hole having a larger diameter than said first hole and an inwardly directed wall surface in at least a portion of the wall between said first and said second ends of said via;
means for electrically insulating the exposed surface of said via between said first and second ends thereof;
an electrically conductive pad surrounding said first hole in each wafer for making an electrical connection to electrical circuits located on said first surface of said wafer;
an electrically conductive compliant material which is located in said via in a wafer and, when not compressed, extends outwardly beyond the plane of said first and said second holes of said via in each wafer so as to make an electrical contact with the electrically conductive pad surrounding said hole and the compliant material in the via of an underlying wafer;
an electrically conductive feedthrough pin mounted in said base plate for making an electrical contact with said electrically compliant material in said via in said wafer located adjacent to said base plate;
and
means located between said top wall and said wafer located adjacent to said top wall for applying pressure to said stack of wafers such that said compliant material in a wafer is compressed against the compliant material in a wafer adjacent thereto for forming an electrically conductive path between said adjacent wafers.

5 more elements

Dependencies are inferred from the claim text.

Description4,306 words

Summary1,989 words

#1. Field of the Invention

#The present invention relates to semiconductor wafer arrays in general and in particular to a method and apparatus comprising a stacked array of semiconductor wafers which are vertically interconnected by means of a plurality of wads of an electrically conductive compliant material.

#2. Description of the Prior Art

Brief description of the drawings15 figures

#The above and other objects, features and advantages of the present invention will become apparent from the following detailed description of the accompanying drawing, in which:

#FIG. 1 is a cross-sectional view of a semiconductor wafer array comprising a plurality of stacked wafers according to the present invention;

#FIG. 2 is a plan view of one of the wafers of FIG. 1 showing several ring-shaped electrical pads on one surface thereof;

Detailed description1,917 words

#Referring to FIG. 1, there is provided in accordance with the present invention a semiconductor wafer array designated generally as 1. In the array 1 there is provided a housing 2 mounted on a base plate 3. In the housing 2 there is provided a plurality of side walls 4, 5 and 6 and a top wall 7. A front wall corresponding to side walls 4-6 is not shown. Located in the housing 2 between the base plate 3 and top wall 7, there is provided a stack of semiconductor wafers 10-18. In the stack of wafers 10-18, the bottom wafer 10 is located adjacent to the base plate 3. The top wafers 18 is located nearest to the top wall 7. Wafer 18 may be a dummy wafer which is used simply for terminating the vertical electrical connecting members and forming an electrical connection with the pads on wafer 17 as will be further described below. On top of wafer 18 between wafer 18 and top wall 17, there is provided a compliant electrically insulating thermally conductive pad 20. Pad 20 is located between the wafer 18 and the top wall 7 to compensate for thermal expansion and contraction of the stack of wafers 10-18 and for conducting heat from the stack of wafers 10-18 to the top wall 7. Extending from the top wall 7 there is provided a plurality of metallic fingers 21. Fingers 21 comprise cooling fins for dissipating heat from the housing 2.

#Extending through the base plate 3 there is provided a plurality of electrical pin members 22. Pin members 22 are provided for making electrical contact with electrically conductive compliant material in vias in the stack of wafers 10-18, as will be further described below.

#In practice, the base plate 3 comprises insulating material, such as ceramic material, for insulating the pin members 22 from each other, and the side wall members 2 and 4 may comprise a metallic material. The free area within the housing 2 may be filled with a conventional electrically non-conductive gaseous or liquid material to facilitate the dissipation of heat from the housing 2.

Facts

Application

07/414,633Filed 28 Oct 1987 · continuation in part

Priority

17 Jul 1986

Granted

4 Sep 1990

Term ended

4 Sep 2007

Estimated · how

Pre-1995 term; greater of 17 years from grant or 20 years from filing when eligible. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification16 codes

H10W 72/00
Interconnections or connectors in packages
H10W 20/023
Of interconnections within wafers or substrates: the interconnections being through-semiconductor vias
H10W 20/0238
The interconnections being through-semiconductor vias: comprising etching via holes through pads or through electrodes
H10W 20/0261
The interconnections being through-semiconductor vias: characterised by the filling method or the material of the conductive fill

Semiconductor wafer array with electrically conductive compliant material

Life of this patent

Semiconductor wafer array with electrically conductive compliant material

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims21

Description4,306 words

Drawings

Classification16 codes

Life of this patent

Description4,306 words