US 4,954,769 AGranted

CMOS voltage reference and buffer circuit

AssigneeBurr-Brown Corporation

InventorTimothy V. Kalthoff

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Abstract

A stable, low noise, low output impedance CMOS reference voltage circuit includes a CMOS/bipolar band gap circuit producing a reference voltage on the source of a source follower transistor driven by an output of a CMOS differential amplifier which maintains a V.sub.THERMAL voltage across the bases of a pair of emitter follower transistors driving the inputs of the CMOS differential amplifier. A power supply noise rejection circuit includes a cascode MOSFET coupling the drain of the source follower output transistor to a positive power supply voltage conductor. A current mirror circuit greatly attenuates any power supply voltage perturbations before they reach the gate of the cascode MOSFET. A unity gain buffer includes a CMOS differential amplifier input stage with one input coupled to the output of the source follower transistor and an output driving a CMOS operational transconductance amplifier.

Claims21

Dependent claims

A voltage reference circuit that is resistant to power supply noise, comprising in combination:

(a) a band gap circuit including first and second transistors having different current densities therein and having a resistor coupled between a base of the first transistor and a base of the second transistor, a first FET differential amplifier circuit having first and second input terminals coupled to an emitter of the first transistor and an emitter of the second transistor, respectively;
(b) a first FET having a gate coupled to an output of the first FET differential amplifier circuit and a source coupled to a first output conductor and producing thereon a first reference voltage;
(c) feedback means coupled to the output of the first FET differential amplifier circuit for applying a portion of the first reference voltage to maintain a V.sub.THERMAL voltage across the resistor equal to the difference between a V.sub.BE voltage of the first transistor and a V.sub.BE voltage of the second transistor so as to maintain equal voltages on the first and second input terminals;
(d) a power supply noise rejection circuit including
i. a second FET having a gate coupled to the output of the first FET differential amplifier circuit and a source coupled to the first output conductor, the second FET having a channel width-to-length ratio substantially less than a channel width-to-length ratio of the first FET,
ii. a first cascode FET coupling a drain of the first FET to a first supply voltage conductor,
iii. a second cascode FET having a source coupled to a drain of the second FET,
iv. a third FET having a source coupled to the first supply voltage conductor, and a gate and a drain coupled to a drain of the second cascode FET,
v. a fourth FET having a source coupled to the first supply voltage conductor and a gate coupled to the gate of the third FET, and a drain coupled to the gate of the first and second cascode FETs,
vi. a fifth FET having a gate and drain coupled to the gate of the first and second cascode FETs and a source coupled to the first output conductor.

7 more elements

A voltage reference circuit that is resistant to power supply noise, comprising in combination:

(a) a band gap circuit including first and second transistors having different current densities therein and having a resistor coupled between a base of the first transistor and a base of the second transistor, a first FET differential amplifier circuit having first and second input terminals coupled to an emitter of the first transistor and an emitter of the second transistor, respectively;
(b) a first FET having a gate coupled to an output of the first FET differential amplifier circuit and a source coupled to a first output conductor and producing thereon a first reference voltage;
(c) feedback means coupled to the output of the first FET differential amplifier circuit for applying a portion of the first reference voltage to maintain a V.sub.THERMAL voltage across the resistor equal to the difference between a V.sub.BE voltage of the first transistor and a V.sub.BE voltage of the second transistor so as to maintain equal voltages on the first and second input terminals;
(d) a power supply noise rejection circuit including
i. a cascode FET coupling a drain of the first FET to a first supply voltage conductor,
ii. a bias circuit connected to the first supply voltage conductor and a gate of the cascode FET to produce a bias voltage on the gate of the cascode FET, the bias circuit including means for attenuating noise on the first supply voltage conductor from reaching the gate of the cascode FET.

3 more elements

A method of producing a stable, low noise reference voltage from a low impedance source, comprising the steps of:

(a) maintaining different current densities in first and second bipolar transistors and maintaining a V.sub.THERMAL voltage across the bases of first and second bipolar transistors by means of a first CMOS differential amplifier with a source follower output FET;
(b) producing a first reference voltage at a source of the source follower output FET;
(c) applying a portion of the first reference voltage across a resistor coupled between bases of the first and second bipolar transistors, emitters of the first and second transistors being coupled to the inputs of the first CMOS differential amplifier, respectively;
(d) rejecting power supply variations from the first reference voltage by
i. coupling a drain of the source follower output FET to a first supply voltage conductor by means of a cascode FET, and
ii. producing a gate voltage of the cascode FET by dividing a voltage difference between the first supply voltage conductor and the first reference voltage conductor so that only a small fraction of any variation of a supply voltage on the supply voltage conductor is coupled to the gate of the cascode FET.

3 more elements

A unity gain buffer circuit having an output conductor, comprising in combination:

i. a FET differential amplifier circuit having an inverting input coupled to the output conductor, and a single ended output conductor;
ii. a FET operational transconductance amplifier having a non-inverting input coupled to the single ended output conductor and an output coupled to an inverting input of the FET differential amplifier circuit and an inverting input of the FET operational transconductance amplifier, wherein the FET differential amplifier circuit includes first and second input FETs having their sources connected together, first and second load devices, a first cascode FET coupling the first load device to a drain of the first input FET, and a second cascode FET coupling the second load device to a drain of the second input FET.

Dependencies are inferred from the claim text.