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AssigneeThe Board of Trustees of the Leland Stanford Junior University
InventorKanji Yoh
Estimating the term…
A merged enhancement/depletion-mode FET circuit and a complementary FET logic circuit have enhanced operation speed and reduced power dissipation. Serially connected depletion mode and enhancement mode transistors function as an output stage for the complementary FET logic stage, with the gate of an n-channel enhancement-mode transistor being connected to the output of the complementary FET logic stage and the output of an n-channel depletion-mode transistor being connected to the common terminal or output terminal of the output stage. In an alternative embodiment, a p-channel enhancement-mode transistor is connected in parallel with the n-channel depletion-mode transistor with the gate of the p-channel enhancement-mode transistor being connected to the output of the complementary FET logic stage. The circuitry is particularly useful in compound semiconductor circuits using MESFETS and heterojunction-FETs.
An FET circuit comprising
For use with a complementary FET circuit, an output circuit comprising a first depletion-mode transistor serially connected with a first enhancement-mode transistor with said serially connected transistors having a common terminal therebetween, said enhancement-mode transistor having a gate electrode connected to an output terminal of the complementary FET circuit, said first depletion-mode transistor having a gate electrode connected to said common terminal, the output terminal of said output circuit being said common terminal.
Dependencies are inferred from the claim text.