Direct digital synthesizer with selectably randomized accumulator
AssigneeHughes Aircraft Company
InventorKenneth A. Essenwanger
Life of this patent
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Abstract
A direct digital synthesizer (DDS) accumulator circuit is disclosed wherein a selected few of the low order accumulator bits are dithered by a pseudorandom number generator in order to introduce flat frequency deviation density to suppress spurious signals including those close-in to the output or fundamental frequency. The accumulator circuit may advantageously be sectioned into a lower order accumulator and higher order accumulator in a pipelined combination with a sine approximation output circuit in order to construct a DDS circuit wherein such spur suppression is achieved without decreasing system throughput.
Claims21
Direct digital frequency synthesis circuitry for use in synthesizing an output having a fundamental frequency from an input phase increment value comprising:
- first adder means having first and second inputs and an output and receiving at least a portion of said phase increment value at said first input;
- storage means having an input and an output;
- and
- means connected to said first adder means and said storage means for producing a signal at said output of said storage means having said fundamental frequency and exhibiting a plurality of spurs located at frequencies spaced apart from said fundamental frequency on each side thereof and for causing said signal to exhibit substantially nonvarying frequency deviation density in the vicinity of said spurs wherein the parameter "frequency deviation density" represents the rms frequency deviation about a frequency f.sub.m measured at the output of an FM discriminator having a baseband filter 1-Hertz wide centered on the frequency f.sub.m.
A direct digital frequency synthesizer (DDS) for producing an output signal including a fundamental frequency and a plurality of spurs comprising:
- accumulator means for producing an accumulated output;
- means connected to said accumulator means for causing said output signal to exhibit nonvarying frequency deviation density in the vicinity of said spurs in said output signal, wherein the parameter "frequency deviation density" represents the rms frequency deviation about a frequency f.sub.m measured at the output of an FM discriminator having a baseband filter 1-Hertz wide centered on the frequency f.sub.m ;
- and
- sine approximation circuit means receiving the output of said accumulator means for converting said accumulated output to an analog output waveform.
Direct digital frequency synthesis circuitry for use in synthesizing an output from an input phase increment value, said output having a fundamental frequency and spurs disposed adjacent said fundamental frequency comprising:
- first adder means having first and second inputs for receiving at least a portion of said phase increment value at said first input and for generating a sum output and an overflow output;
- storage means having an input and an output connected to one of said first and second inputs of said first adder means;
- a second adder means having first and second inputs and an output, said first input of said second adder means being connected to receive the sum output of said first adder means, the output of said second adder means being connected to the input of said storage means;
- a pseudorandom number generator means for generating and outputting a pseudorandom number;
- and
- an enable gate means receiving said pseudorandom number from said generator means and said overflow output from said first adder means for supplying said pseudorandom number to the second input of said second adder means in response to generation of a said overflow output.
Direct digital frequency synthesizing circuitry for use in generating an output to be received by a sine approximation circuit means and containing a fundamental frequency wherein said fundamental frequency is determined by a frequency control word, comprising:
- a lower order accumulator means receiving a selected number of the lower order bits of said frequency control word and a second input and supplying an accumulated output comprising a plurality of bits and a carry output;
- dither generator means receiving said plurality of bits and a carry input for dithering a selected number of said plurality of bits and supplying a dithered output as said second input to said lower order accumulator means;
- and
- a higher order accumulator means receiving a selected number of the higher order bits of said frequency control word and said carry output for generating said carry input and the said output received by said sine approximation circuit means and and for supplying said carry input to said dither generator means.
Dependencies are inferred from the claim text.