EEPROM utilizing single transistor per cell capable of both byte erase and flash erase

Circuit comprising:

• a first region of semiconductor material;
• an array of floating gates organized into rows and columns, each of said floating gates being formed above but insulated from said first region of semiconductor material, each row of floating gates being organized into groups of floating gates within said row;
• a plurality of control gate leads, each control valve lead being associated with one of said rows of floating gates, wherein each control gate lead extends over but is insulated from the floating gates within the associated row of floating gates;
• a plurality of common source/drain regions formed within said first region of semiconductor material such that each common source/drain region is bordered on a first side by a first group of said floating gates from one of said rows while a second side is bordered by another group of said floating gates from another of said rows;
• a plurality of source/drain regions formed within said first region of semiconductor material adjacent at least one of said floating gates such that each floating gate separates an associated one of said source/drain regions within said plurality from one of said common source/drain regions;
• means for applying an erase voltage to said common source/drain regions in a first mode and a second mode such that in said first mode, all of said common source/drain regions simultaneously receive said erase voltage so that all of said floating gates are simultaneously erased, and in said second mode, fewer than all of said common source/drain regions receive said erase voltage so that fewer than all of said floating gates are erased.