US 4,949,301 A · Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM's address inputs

An apparatus for controlling the address inputs of a memory, comprising:

first means for storing a plurality of address pointers;
second means coupled to said first means for selecting one of said address pointers and for outputting said selected address pointer to said memory;
third means coupled to said second means and to said first means for incrementing the selected address pointer and loading it back into said first means to replace the selected address pointer;
wherein said first means stores a write address pointer and read address pointer for receiving packets to be stored in said memory and a read address pointer and a write address pointer for transmit packets to be retrieved from said memory for transmision, said receive packets and transmit packets being received from and/or sent to said accessing devices;
further comprising an initialization bus coupled to said first means, and fourth means coupled to said initialization bus and said first means for receiving and storing starting address pointers on said initialization bus and said initialization bus for allowing independent setting of any of said address pointers to a selected address, and said fourth means also for causing said starting address pointers to be stored in said first means at predetermined times, wherein said first means includes a plurality of registers for storing said address pointers including a first register for storing a write pointer for receive packets and having an output coupled to said second means and a second register for storing a shadow write pointer for receive packets where said first and second registers have inputs and outputs, and further comprising first and second multiplexers having outputs coupled respectively to said inputs of said first and second registers, each said multiplexer having a plurality of inputs wherein one input of said first multiplexer is coupled to said third means for receiving the incremented value of said write pointer for receive packets when said second means selects the write pointer for receive packets for output to said memory and wherein the output of said second register is coupled to an input of each of said first and second multiplexers and wherein the output of said first register is coupled to an input of each of said first and second multiplexers.

2 more elements

An apparatus for controlling the address inputs of a memory, comprising:

first means for storing a plurality of address pointers;
second means coupled to said first means for selecting one of said address pointers and for outputting said selected address pointer to said memory;
third means coupled to said second means and to said first means for incrementing the selected address pointer and loading it back into said first means to replace the selected address pointer;
wherein said memory includes a first stack and a second stack and said third means is also for decrementing the selected address pointer, further comprising means coupled to said first means for independently initializing separate write and read pointers for said first stack and for initializing separate write and read pointers for said second stack and for controlling said third means to manage the incrementing and decrementing of said write and read pointers such that a last-in, first-out memory access operation in said memory may be performed, wherein said first means includes a plurality of registers for storing said address pointers including a first register for storing a write pointer for receive packets and having an output coupled to said second means and a second register for storing a shadow write pointer for receive packets where said first and second registers have inputs and outputs, and further comprising first and second multiplexers having outputs coupled respectively to said inputs of said first and second registers, each said multiplexer having a plurality of inputs wherein one input of said first multiplexer is coupled to said third means for receiving the incremented value of said write pointer for receive packets when said second means selects the write pointer for receive packets for output to said memory and wherein the output of said second register is coupled to an input of each of said first and second multiplexers and wherein the output of said first register is coupled to an input of each of said first and second multiplexers.

1 more element

An apparatus for controlling the address inputs of a memory, comprising:

first means for storing a plurality of address pointers;
second means coupled to said first means for selecting one of said address pointers and for outputting said selected address pointer to said memory;
third means coupled to said second means and to said first means for incrementing the selected address pointer and loading it back into said first means to replace the selected address pointer;
wherein said first means stores a write address pointer and read address pointer for receiving packets to be stored in said memory and at least two read address pointers and a write address pointer for transmit packets to be retrieved from said memory for transmission;
and
wherein said first means includes a plurality of registers, each said register for storing one of said address pointers, one of said registers for storing the read address pointer for transmit packets, and further comprising linked list means, connected to said first means, for receiving and storing at least two separate and independent link pointers for at least two separate and independent linked lists as said at least two read address pointers for said transmit packets.

3 more elements

An apparatus for controlling the address inputs of a memory, comprising:

first means for storing a plurality of address pointers;
second means coupled to said first means for selecting one of said address pointers and for outputting said selected address pointer to said memory;
third means coupled to said second means and to said first means for incrementing the selected address pointer and loading it back into said first means to replace the selected address pointer;
wherein said first means comprises a plurality of registers for storing said address pointers and further comprises a plurality of multiplexers each having an output, with one said multiplexer output coupled to a data input of a respective one of said plurality of registers, and each said multiplexer having a plurality of inputs including first inputs and second inputs, and further comprising an initialization bus coupled to said first inputs and wherein said third means is coupled to said second inputs, where said plurality of registers includes a first register for storing a write pointer for receive packets and having an output coupled to said second means and a second register for storing a shadow write pointer for receive packets, where said first and second registers have inputs and outputs, and wherein said plurality of multiplexers includes first and second multiplexers having outputs coupled, respectively, to said inputs of said first and second registers, each of said first and second multiplexers having a plurality of inputs, wherein one input of said first multiplexer is coupled to said third means for receiving the incremented value of said write pointer for received packets for output to said memory, and wherein the output of said second register is coupled to an input of each of said first and second multiplexers and wherein the output of said first register is coupled to an input of said first and second multiplexers.

1 more element

An apparatus for controlling the address inputs of a memory, comprising:

first means for storing a plurality of address pointers;
second means coupled to said first means for selecting one of said address pointers and for outputting said selected address pointer to said memory;
third means coupled to said second means and to said first means for incrementing the selected address pointer and loading it back into said first means to replace the selected address pointer;
wherein said first means includes a plurality of registers for storing said address pointers including a first register for storing a write pointer for receive packets and having an output coupled to said second means and a second register for storing a shadow write pointer for receive packets where said first and second registers have inputs and outputs, and further comprising first and second multiplexers having outputs coupled respectively to said inputs of said first and second registers, each said multiplexer having a plurality of inputs wherein one input of said first multiplexer is coupled to said third means for receiving the incrmented value of said write pointer for receive packets when said second means selects the write pointer for receive packets for output to said memory and wherein the output of said second register is coupled to an input of each of said first and second multiplexers and wherein the output of said first register is coupled to an input of each of said first and second multiplexers.

1 more element

An apparatus for controlling the address inputs of a memory, comprising:

first means for storing plurality of address pointers;
second means coupled to said first means for selecting one of said address pointers and for outputting said selected address pointer to said memory;
third means coupled to said second means and to said first means for incrementing the selected address pointer and loading it back into said first means to replace the selected address pointer;
further comprising arbitration means coupled to said second means and having a plurality of service request signal inputs from said accessing devices for receiving signals indicating that a particular pointer is desired to be selected, said arbitration means for arbitrating said request signals and selecting the currently asserted request with the highest priority;
wherein said first means includes a plurality of registers for storing said address pointers including a first register for storing a write pointer for receive packets and having an output coupled to said second means and a second register for storing a shadow write pointer for receive packets where said first and second registers have inputs and outputs, and further comprising first and second multiplexers having outputs coupled respectively to said inputs of said first and second registers, each said multiplexer having a plurality of inputs wherein one input of said first multiplexer is coupled to said third means for receiving the incremented value of said write pointer for receive packets when said second means selects the write pointer for receive packets for output to said memory and wherein the output of said second register is coupled to an input of each of said first and second multiplexers and wherein the output of said first register is coupled to an input of each of said first and second multiplexers;
and
further comprising a clock input of receiving a clock signal and wherein said second means has a control input and wherein said first means comprises a plurality of registers for storing predetermined ones of said pointer addresses, each register having an input and an output and a clock input for receiving said clock signal for causing the data at said input to be latched into said register and to be available for output on said output, and further comprising a plurality of multiplexers each having its output coupled to a said input of one of said registers and each having at least one input coupled to the output of the register to which the multiplexer has its output coupled, and wherein said third means has an output carrying the incremented value of the pointer selected by said second means, said output of said third means coupled to another input of each said multiplexer, and each said multiplexer having a control input, and further comprising a control means coupled to said control inputs of said multiplexers and to said arbitration means and to a control input of said second means for sensing which request signal has received priority and for causing said second means to select the appropriate one of said pointers in accordance with the result of the arbitration and for causing said multiplexer coupled to the input of the reigster whose pointer contents have been selected for output by said second means to select its input coupled to the output of said third means for a first clock cycle and for causing said multiplexer input coupled to the selected register to select the multiplexer input coupled to the output of the selected register during a second clock cycle.

4 more elements

An apparatus for controlling the address inputs of a memory, comprising:

first means for storing a plurality of address pointers;
second means coupled to said first means for selecting one of said address pointers and for outputting said selected address pointer to said memory;
third means coupled to said second means and to said first means for incrementing the selected address pointer and loading it back into said first means to replace the selected address pointer;
wherein said first means includes a plurality of registers for storing said pointers and further comprises an initialization bus coupled to an input of each register and wherein one of said registers is for storing a random access address pointer which can be set initially by said data on said initialization bus and will be incremented by said third means when said random access pointer is selected for output by said second means;
where said plurality of registers includes a first register for storing a write pointer for receive packets and having an output coupled to said second means and a second register for storing a shadow write pointer for receive packets, where said first and second registers have inputs and outputs, and further comprising first and second multiplexers having outputs coupled, respectively, to said inputs of said first and second registers, each of said first and second multiplexers having a plurality of inputs, wherein one input of said first multiplexer is coupled to said third means for receiving the incremented value of said write pointer for receive packets for output to said memory, and wherein the output of said second register is coupled to an input of each of said first and second multiplexers and wherein the output of said first register is coupled to an input of said first and second multiplexers.

2 more elements

An apparatus for generating address pointers at an output for coupling to an address port of a memory for controlling data operations of said memory comprising:

a clock means for periodically generating a load signal;
a first register means having an input and having a load input coupled to said clock means for storing the address at said input upon each occurrence of said load signal and having an output, said register means for storing a read pointer for a transmit FIFO;
a second register means having an input and having a load input coupled to said clock means for storing the address at said input upon each occurrence of said load signal and having an output, said register means for storing a write pointer for said transmit FIFO;
a third register means having an input and having a load input coupled to said clock means for storing the address at said input upon each occurrence of said load signal and having an output, said register means for storing a read pointer for a receive FIFO;
a fourth register means having an input and having a load input coupled to said clock means for storing the address at said input upon each occurrence of said load signal and having an output, said register means for storing a write pointer for said receive FIFO;
an output multiplexer having inputs coupled to said outputs of said first, second, third and fourth register means and having an output and having a control input for receiving a signal controlling which of said inputs is coupled to said output;
first through fourth input multiplexers for said first through fourth register means, respectively, each input multiplexer having an output coupled to said input of an associated register means and each input multiplexer having first and second inputs and having a control input for receciving a signal controlling which of said inputs is coupled to said outputs;
an incrementing means having an input coupled to the output of said output multiplexer and having an output coupled to each first input of each said input multiplexer, for incrementing the address pointer at the output of said output multiplexer and for supplying the incremented result to said first inputs of said first through fourth input multiplexers;
an initialization bus coupled to each second input of said input multiplexers for allowing any of said registers to be loaded with an address placed on said initialization bus;
control means having an instruction port and having output signal lines coupled to said control inputs for said input multiplexers to cause any selected one of said input multiplexers to select the selected input multiplexers second input for coupling to said output of said selected input multiplexer when a predetermined instruction arrives at said instruction port;
and
arbitration means having a plurality of memory access request inputs and having a plurality of control signal lines coupled to said control inputs of said input multiplexers and to said control input of said output multiplexer for arbitrating simulataneous memory access requests with each said request associated with one of said register means, for selecting the highest priority current memory access request and for activating predetermined control signal lines to cause said output multiplexer to select the output of the register means associated with the current highest priority memory access request selected by said arbitration means for output by said output multiplexer and for causing the input multiplexer coupled to the associated register means to select the input coupled to said incrementing means such that the current address in the selected register means will be incremented and the new value will be loaded on the next clock cycle.

9 more elements

A method of operating a RAM buffer controller controlling the address inputs of a memory, said RAM buffer controller being coupled to an output of a data path controller and having a first register for storing write pointer addresses for use in storing received packets from a network in said memory and having a second register for storing a shadow write pointer and having first and second multiplexers controlling the data which is input respectively to said first register and to said second register and having an incrementer having an input and having an output coupled to an input of said first multiplexer where said first multiplexer also has inputs coupled to the output of said first register and to the output of said second register and where said second multiplexer has inputs coupled to the output of said first register and to the output of said second register and having control logic with a plurality of input signal lines and a plurality of output control lines to control the operation of said first and second multiplexers by means of a control program where each of said first and second multiplexers has a clock input coupled to a clock generating load signals and having an output multiplexer with a plurality of inputs including an input coupled to the output of said first register and with an output coupled to the input of said incrementer comprising the steps of:

generating signals by said control logic according to said control program upon receipt of a first signal from said data path controller to cause said second multiplexer to select its input coupled to the output of said first register and to cause the contents of said first register to be stored in said second register and thereafter generatng signals according to said control program to cause said second multiplexer to select its input coupled to the output of said second register and generating control signals according to said control program to cause said first multiplexer to select its input coupled to said incrementer and thereafter generating signals according to said control program causing said first multiplexer to select its input coupled to the output of said first register;
generating signals by said control logic according to said control program upon receipt of a second signal from said data path controller to cause said output multiplexer to select the input coupled to the output of said first register once during every memory cycle and to cause said first multiplexer to again select its input coupled to said incrementer on every memory access cycle and thereafter to hold the contents of said first register constant by selecting the input coupled to the output of said second register between memory cycles, and generating signals to cause said second multiplexer to select its input coupled to the output of said second register while said first multiplexer is selecting its input coupled to said incrementer;
generating signals by said control logic according to said control program upon receipt of a third signal from said data path controller to cause said second multiplexer to select its input coupled to the output of said first register and to cause the contents of said first register to be stored in said second register and to cause the contents of said second register to thereafter be held constant for a predetermined period and simultaneously with the loading of the contents of said first register into said second register to cause said first multiplexer to select its input coupled to the output of said second register and to cause the contents of said second register to be stored in said first register and thereafter to cause the contents of said first register to be held constant for another predetermined period;
generating signals according to said control program to cause said output multiplexer to select the input coupled to the output of said first register and writing status and length information into the memory location in said memory addressed by the contents of said first register;
generating signals according to said control program cuasing said first multiplexer to select its input coupled to the output of said second register so that the contents of said second register will be loaded into said first register and to cause the contents of said first register to be held constant;
writing a predetermined bit into the memory location addressed by the contents of said first register;
and
generating signals according to said control program causing said first multiplexer to select its input coupled to the output of said first register to hold the contents of said first register constant.

5 more elements

A method of operating a RAM buffer controller controlling the address input of a memory, said RAM buffer controller being coupled to an output of a data path controller, and having a first register for storing write pointer addresses for use in storing received data in said memory, and having a second register for storing a shadow write pointer, and having first and second multiplexers controlling the data which is input respectively to said first register and to said second register, and having an incrementer having an input and having an output coupled to an input of said first multiplexer and wherein said first multiplexer also has input coupled to the output of said first register and to the output of said second register, and wherein said second multiplexer has inputs coupled to the output of said first register and to the output of said second register, and having control logic with a plurality of input signal lines and a plurality of output control lines to control the operation of said first and second multiplexers by means of a control program where each of said first and second multiplexers has a clock input coupled to a clock, said clock for generating load signals, and having an output multiplexer with a plurality of inputs including an input coupled to the output of said first register and an output coupled to the input of said incrementer, comprising the steps of:

generating signals by said control logic according to said control program upon receipt of a first signal from said data path controller to cause said second multiplexer to select its input coupled to the output of said first register and to cause the contents of said first register to be stored in said second register, and, thereafter, generating signals according to said control program to cause said second multiplexer to select its input coupled to the output of said second register, and generating control signals according to said control program to cause said first multiplexer to select its input coupled to said incrementer, and, thereafter, generating signals according to said control program causing said first multiplexer to select its input coupled to the output of said first register;
generating signals by said control logic according to said control program upon receipt of a second signal from said data path controller to cause said output multiplexer to select the input coupled to the output of said first register once during every memory cycle and to cause said first multiplexer to again select its input coupled to said incrementer on every memory access cycle, and, thereafter, to hold the contents of said first register constant by selecting the input coupled to the output of said first register between memory cycles, and generating signals to cause this second multiplexer to select its input coupled to the output of said second register while said first multiplexer is selecting its input coupled to said incrementer;
generating signals by said control logic according to said control program upon receipt of a third signal from said data path controller to cause said first multiplexer to select its input coupled to the output of said second register and to cause the contents of said second register to be stored in said first register, and, thereafter, to cause the contents of said first register to be held constant for a predetermined period.

Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM's address inputs

Life of this patent

Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM's address inputs

Life of this patent

Abstract

Claims40