Static method to negate offset voltages in CMOS operational amplifiers

A circuit arrangement for adjusting offset voltages associated with operational amplifiers, said circuit arrangement comprising in combination:

• a first operational amplifier:
• a first input stage coupled to said operational amplifier;
• said input stage providing a first offset voltage having a magnitude which is greater than the magnitude of a natural offset voltage of said operational amplifier;
• a control means coupled to said input stage said control means providing a control voltage so that the algebraic sum of the first offset voltage, the control voltage and the natural offset voltage is essentially zero;
• a second operational amplifier having an output terminal, a positive and negative input terminals;
• a current source;
• a first FET device coupled to the negative input terminal and the current source;
• a second FET device coupled to the current source and arranged in parallel with the first FET;
• a first conductor coupling the second FET device with the output terminal;
• a second conductor interconnecting said second FET device to the positive input terminal;
• and
• a third conductor interconnecting a substrate electrode of said first FET device to the first operational amplifier.

A circuit arrangement for generating a control signal for negating offset voltages associated with CMOS operational amplifiers comprising:

• an operational amplifier which generates the control voltage;
• said operational amplifier having an output node, a negative input node and a positive input node;
• a current source;
• a first FET device having a source electrode connected to the current source and a drain electrode connected to the negative input node and a substrate electrode connected to the output node;
• a second FET device placed in parallel with the first FET device, said second FET device having a substrate and source electrode connected to the current source and a drain electrode connected to the positive input node;
• and
• a circuit network for biasing the first FET device and second FET device coupled to the gate electrode of said first and second FET device.