Circuit arrangement for averaging signals during pulse-density D/A or A/D conversion
AssigneeDeutsche ITT Industries GmbH
InventorsHeinrich Pfeifer, Werner Reich, Ulrich Theus
Life of this patent
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Abstract
In a pulse-density D/A or A/D converter, improved averaging of a pulse-density-modulated (PDM) signal in the presence of a jittering clock signal is achieved by applying the PDM signal to the serial input of an n-stage shift register whose parallel output serves to control n state signals. The shift register is driven by the clock signal. The n state signals are combined into a sum signal which feeds a low-pass filter. In preferred embodiments, the n state signals are weighted and/or isolated from the respective previous state and the following state by means of gate circuits.
Claims13
A circuit that averages a pulse-density-modulated signal, comprising;
- a shift register having n stages, said shift register having a serial input and a clock input, and having an output from each of said n stages, said serial input being fed with said pulse-density-modulated signal, said clock input being fed with a clock signal;
- a summer fed with n state signals, each of said state signals being assigned to and dependent on the state of the output of one of said n shift register stages, said summer providing a sum output signal responsive to said state signals;
- and
- a low-pass filter having an input and an output, said input connected to the sum output from said summer, said low-pass filter providing the averaged signal at its output.
Dependencies are inferred from the claim text.