US 4,947,169 AGranted

Dummy/trim DAC for capacitor digital-to-analog converter

AssigneeBurr-Brown Corporation

InventorsLewis R. Smith, David M. Thomas

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Abstract

In one embodiment, a successive approximation analog-to-digital converter having a main CDAC and a trim CDAC includes resistors in the main CDAC connected in series with various bit switch FETs. The resistors are precisely matched to equivalent resistances of trimmable voltage divider circuits connected in series with various corresponding bit switch FETs in the trim DAC, to prevent non-linear parasitic capactiance and voltage-current properties of first and second clamping FETs from "unbalancing" the voltages on the charge summing conductors of the main DAC and the trim DAC during turn-off of the first and second clamping FETs after they have been turned on to equalize the voltages of the charge summing conductors. In another embodiment, separate trim and dummy DACs are provided to improve the accuracy to which the resistances in the main CDAC and trim CDAC can, as a practical matter, be matched.

Claims20

Dependent claims

A method of improving the offset voltage of an analog-to-digital converter including a first CDAC and a second CDAC, the method comprising the steps of:

(a) turning on first and second FETs to charge a first charge summing conductor in the first CDAC to a first reference voltage and to charge a second charge summing conductor in the second CDAC to the first reference voltage, respectively;
(b) turning on a first sampling FET in the first CDAC, while the first and second FETs are on and charging a most significant capacitor in the first CDAC through the first sampling FET to an analog input voltage;
(c) turning the first and second FETs off by means of a control signal with a turn-off transition time, the first and second FETs each exhibiting substantially nonlinear parasitic capacitances and substantially nonlinear voltagecurrent properties;
(d) during step (c)
i. causing parasitic currents produced by the turning off of the first FET as a result of the nonlinear parasitic capacitances and the nonlinear voltage-current properties thereof to flow through a plurality of capacitors in the first CDAC and through a plurality of parasitic capacitances of a plurality of bit switch circuits in the first CDAC and through a plurality of resistors connected in series with the bit switches of the first CDAC, respectively,
ii. simultaneously with (i), causing parasitic currents produced by turning off of the second FET as a result of the nonlinear parasitic capacitances and the nonlinear voltage-current properties thereof to flow through a plurality of capacitors in the second CDAC and through a plurality of parasitic capacitances of a plurality of bit switch circuits in the second CDAC and through equivalent resistances of a plurality of resistive voltage dividers connected in series with the bit switches, respectively, of the second CDAC, corresponding channel resistances of the corresponding bit switch circuits of the first and second CDACs being matched, the binarily weighted capacitors of the first and second CDACs being matched, and the resistors of the first CDAC being matched to the equivalent resistances of resistive voltage divider circuits, respectively,
to thereby cause the voltages on the first and second charge summing conductors to be substantially equal at the end of the turn-off transition time of the control signal despite the nonlinear parasitic capacitances and nonlinear voltage-current properties of the first and second FETs;
and
(e) turning the first sampling FET off.

6 more elements

In a successive approximation analog-to-digital converter, CDAC circuitry comprising in combination:

(a) a first CDAC including
i. a first charge summing conductor,
ii. a first group of binarily weighted capacitors each having a first terminal coupled to the first charge summing conductor,
iii. a first group of bit switch circuits each including an output coupled to a second terminal of a corresponding capacitor of the first group, each bit switch circuit including a pullup FET having a gate coupled to receive a corresponding digital input bit signal, a drain coupled by a first resistor to a first reference voltage, and a source coupled to the output of that bit switch circuit, each bit switch circuit including a pulldown FET having a gate coupled to receive a complement of the digital input bit signal, a source coupled by a second resistor to a second reference voltage, and a drain coupled to the output of that bit switch circuit;
(b) a second CDAC including
i. a second charge summing conductor,
ii. a second group of binarily weighted capacitors each having a first terminal coupled to the second charge summing conductor,
iii. a second group of bit switch circuits each including an output coupled to a second terminal of a corresponding capacitor of the second group, each bit switch circuit of the second group including a pullup FET having a gate coupled to receive a corresponding digital input bit signal, a source coupled to the output of that bit switch circuit, each bit switch of the second group including a pulldown FET having a gate coupled to receive a complement of the digital input bit signal, a source coupled by a first resistor to the second reference voltage, and a drain coupled to the output of that bit switch circuit, each bit switch circuit of the second group including a trimmable resistive voltage divider circuit including a second resistor coupled between the first reference voltage and a drain of the pullup FET of that bit switch circuit and a third resistor coupled between the drain of the pullup FET of that bit switch circuit and the second reference voltage conductor,
each of the capacitors of the first group being matched to a corresponding capacitor of the second group, the resistance of the first resistor of each bit switch circuit of the first group being equal to the equivalent resistance of the second and third resistors of the voltage divider of a corresponding bit switch circuit of the second group.

6 more elements

In a successive approximation analog-to-digital converter, CDAC circuitry comprising in combination:

(a) a main CDAC including
a first charge summing conductor, and a first clamping FET coupled between a clamp voltage and the first charge summing conductor,
a first group of binarily weighted capacitors coupled to the first charge summing conductor,
a first group of bit switch circuits coupled to the capacitors, respectively, the bit switch circuits electrically coupling the capacitors, respectively, to either of two voltage levels during a conversion cycle of the analog-to-digital converter,
a sampling switch coupling an analog input voltage through a source resistance to a most significant binarily weighted capacitor during a sample cycle of the analog-to-digital converter,
(b) a dummy CDAC including
a second charge summing conductor and a second clamping FET coupled between the clamp voltage and the second charge summing conductor,
a second group of binarily weighted capacitors coupled to the second charge summing conductor,
a second group of bit switch circuits coupled to the capacitors, respectively, the bit switch circuits electrically coupling the capacitors, respectively, to fixed reference voltage,
a sampling switch coupling the ground voltage through a matched source resistor to a most significant capacitor of the second group during the sample cycle,
(c) a trim CDAC including
a third group of binarily weighted capacitors and coupling means for coupling the third group of binarily weighted capacitors to one of the first and second charge summing conductors,
a third group of bit switch circuits coupled to the capacitors of the third group, respectively,
a group of resistive voltage dividers coupled to the bit switch circuits of the third group, respectively, the bit switch circuits of the third group electrically coupling the capacitors of the third group in series with the resistive voltage dividers, respectively, during the conversion cycle,
whereby voltages on the first and second charge summing conductors are substantially equal after turning the first and second clamping FETs off despite non-linear gate capacitances and voltage-current properties of the first and second clamping FETs and ratio mismatches between successive capacitors of the first group are compensated for by injection of minute amounts of charge established by the various voltage dividers into or out of the one of the first and second charge summing conductors to which the trim CDAC is coupled.

12 more elements

Dependencies are inferred from the claim text.