Linear jitter attenuator

A jitter attenuator for attenuating jitter on an external clock signal, comprising:

• a clock generator for generating a reference clock, said reference clock having a variable frequency that is variable in discrete steps in response to receiving a digital input error correction signal;
• receive means for receiving the external clock signal;
• a phase comparator for comparing the phase of said clock generator and the phase of the external clock and determining the phase difference therebetween for multiple 2.pi. intervals of the phase difference to output a phase error value representative of the absolute phase difference between the received external clock and said clock generator;
• lock means for generating said digital error correction signal for controlling the frequency of said clock generator to maintain said phase error value at a predetermined average phase error, the magnitude of the variation in frequency of said clock generator being a function of the amount that the magnitude of said phase error value, as determined by said phase comparator, varies from said predetermined average phase error, said lock means operable to attenuate phase variations of said clock generator relative to phase variations in said received external clock;
• and
• means for linearizing said clock means to vary the frequency of said clock generator in a stepwise linear manner relative to the variation in said phase error value over the range of variation of said clock generator.

A method for attenuating jitter on a received clock and associated received data, comprising:

• temporarily storing the data in an elastic store device by inputting the received data thereto at the received clock rate, the received clock comprising a Write clock, and outputting the stored data at a separate clock rate generated by a Read clock;
• generating the Read clock which has a frequency that varies in discrete steps in response to receiving a digital control signal, each of the discrete steps being substantially equal;
• determining the phase difference between the Write clock and the Read clock;
• controlling the frequency of the Read clock to maintain the average phase difference at a static difference by varying the value of the digital control signal, each discrete value of the digital control signal representing a finite amount of the phase difference, the magnitude of the variation in frequency of the Read clock being a function of the amount that the magnitude of the phase difference varies from the static difference, the step of controlling the frequency operable to attenuate phase variations of the Read clock relative to phase variations in the Write clock;
• and
• the variations of the frequency of the Read clock relative to the phase error being substantially linear.