US 4,939,687 AGranted

Serial-parallel multipliers using serial as well as parallel addition of partial products

AssigneeGeneral Electric Company

InventorsRichard I. Hartley, Sharbel E. Noujaim

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Abstract

A cell module which is particularly employable in bit-serial silicon compilation methods permits the fabrication and layout of bit-serial multipliers having variable word sizes. In particular, the cell module permits the fabrication of a bit-serial multiplier which is capable of a number of different functions including the production of high-order (major) and low-order (minor) output product bit streams which may be selected from so as to provide output results in a variety of different formats associated with binary fractional multiplication.

Claims31

Dependent claims

A serial-parallel digital multiplier comprising:

means for supplying k bits of a multiplicand signal in parallel during an earlier of two consecutive successions of clock intervals, each n in number, k being an integer greater than one and n being a positive integer at least as large as k;
a battery of two-input port AND gates, k in number, having respective first input ports, respective second input ports, and respective output ports;
means for applying to the first input ports of said battery of AND gates, during each of said earlier succession of clock intervals except its last clock interval, k bits corresponding to respective bits of said multiplicand signal;
means for applying to the first input ports of said battery of AND gates during the last of said earlier succession of clock intervals, k bits that are the one's complement of respective bits of said multiplicand signal;
means for supplying to the second input ports of said battery of AND gates n successive bits of a bit-serial multiplier signal of bit length n as sequentially received during respective ones of said earlier succession of clock intervals, whereby the partial products of each of these bits with the signal applied to the first ports of said AND gates are successively generated at the output ports of said battery of AND gates during respective ones of said earlier succession of clock intervals;
a parallel adder, composed of k bit slices, for adding each successively generated partial product as a first addend to respective second and third addends to generate for each of said k bit slices a respective sum bit and a respective carry bit;
means for supplying during said earlier succession of clock signals a minor product signal obtained from the successive sum bits for the least significant of said k bit slices of said parallel adder;
means for delaying by one clock interval the sum bits generated by the parallel adder for the other, more significant ones of its k bit slices, to generate except for sign bit each successive said second addend for said parallel adder during said earlier succession of clock intervals;
means for applying during the last of said earlier succession of clock intervals a ZERO as the sign bit of said second addend;
means for applying during all other clock intervals in said earlier succession except the first, the sum bit generated in the most significant bit slice of said parallel adder and delayed by one clock interval as the sign bit of said second addend;
means for delaying by one clock interval the carry bits generated by the parallel adder to generate each successive said third addend for said parallel adder during said earlier succession of clock intervals;
first parallel-to-serial converting means for converting the sum bits supplied from said k bit slices of said parallel adder during the last of said earlier succession of clock intervals to appear serially during that clock interval and the ensuing next (k-1) clock intervals in a later of said two consecutive successions of clock intervals, to be followed by a ZERO the next clock interval of said later succession, to be followed by a repeat of the most significant of the sum bits for each remaining one of the n clock intervals of said later succession;
second parallel-to-serial converting means for converting the carry bits supplied from the k bit slices of said parallel adder during the last of said earlier succession of clock intervals to appear serially the ensuing next k clock intervals in said later succession, to be followed by a repeat of the most significant of the carry bits for any remaining one of the n clock intervals of said later succession;
and
a serial adder for adding the sum bits supplied serially by said first parallel-to-serial converting means, the carry bits supplied serially by said second parallel-to-serial converting means, and the sign bit of said bit-serial multiplier signal during the last of said ensuing next k clock intervals of said later succession, thereby to generate a major product signal.

12 more elements

A serial-parallel multiplier comprising:

a battery of two-input-port AND gates, k in number having respective first input ports, having respective second input ports, and having respective output ports, k being an integer greater than one;
means for supplying k bits of a multiplicand signal in parallel to respective ones of the first input ports of said battery of two-input-port AND gates during an earlier of two consecutive successions of clock cycles, each n in number, n being a positive integer at least as large as k;
means for supplying to the second input ports of said battery of AND gates successive bits of a serial multiplier signal of bit-length n as sequentially received in order of increasing bit significance during respective ones of said earlier succession of clock cycles, n in number, whereby the partial products of each of those bits with the multiplicand signal are successively generated at the output ports of said battery of AND gates during respective ones of said earlier succession of clock intervals;
a parallel adder, composed of k bit slices, for adding each successive partial product as a first addend to respective second and third addends to generate for each of said k bit slices a respective sum bit and a respective carry bit;
means for supplying a minor product signal obtained from the successive sum bits for the least significant of the k bit slices of said parallel adder;
means for delaying by one clock interval the sum bits generated by the parallel adder for the other, more significant ones of its k bit slices to generate the less significant bits of said second addend for said parallel adder during said earlier succession of clock intervals;
means for applying a ZERO as the most significant bit of each successive second addend;
means for delaying by one clock interval the carry bits generated by the parallel adder to generate each successive said third addend for said parallel adder during said earlier succession of clock intervals;
first parallel-to-serial converting means for converting the sum bit supplied from the k bit slices of said parallel adder during the last of said earlier succession of clock intervals to appear serially during that clock interval and the ensuing next (k-1) clock intervals of a later of said two consecutive successions of clock intervals to be followed by a ZERO each remaining one of the n clock intervals of said later succession;
second parallel-to-serial converting means for converting the carry bits supplied from the k bit slices of said parallel adder during the last of said earlier succession of clock intervals to appear serially the ensuing next k clock intervals of said later succession, to be followed by a ZERO for any remaining one of the n clock intervals of said later succession;
and
a serial adder for adding the sum bits supplied serially by said first parallel-to-serial converting means, and the carry bits supplied serially by said second parallel-to-serial converting means, thereby to generate a major product signal.

9 more elements

A cell module for a serial-parallel multiplier, said cell module comprising:

an input latch responsive to a control signal switching from a first state thereof to a second state thereof for storing a next occurring single bit of a first to two serial binary operands;
means for deriving a multiplicand bit from the single bit stored in said input latch;
means for multiplying said multiplicand bit by each successive bit of a second of said serial binary operands during a respective clock interval to generate a respective single-bit products;
adder means for adding together during each said clock interval a previous carry output signal from said adder means, the currently generated said single-bit product and a partial sum input bit to said cell module, thereby to generate a current carry bit and a current sum bit;
first unit-delay means for storing said current sum bit for one clock interval, thereby to provide a delayed sum bit selectively supplied from said cell module as a partial sum output bit;
second unit-delay means for storing a single-bit input sum signal supplied to said cell module for one clock interval, thereby to provide a delayed input sum signal;
first selector means, for selecting as a sum output signal from said cell module either said sum bit or said delayed input sum signal;
third unit-delay means for storing a single bit for one clock interval as a carry output signal;
and
second selector means, for selecting to said third unit-delay means for storage, said current carry input signal bit to said cell module.

7 more elements

A cell module for a serial-parallel multiplier, said cell module comprising:

an input latch responsive to a control signal switching from a first state thereof to a second state thereof for storing a next occurring single bit of a first of two serial binary operands;
means for deriving a multiplicand bit from the single bit stored in said input latch;
means for multiplying said multiplicand bit by each successive bit of a second of said serial binary operands during a respective clock interval to generate a respective single-bit product;
first unit-delay means for storing a partial sum input bit to said cell module for one clock interval, thereby to provide a delayed partial sum input bit;
adder means for adding together during each said clock interval its own previous carry output signal, the currently generated aid single-bit product and said delayed partial sum input bit, thereby to generate a current carry bit and a current sum bit;
second unit-delay means for storing a single-bit input sum signal supplied to said cell module for one clock interval, thereby to provide a delayed input sum signal;
means for selecting as a sum output signal from said cell module either said sum bit or said delayed input sum signal;
third unit-delay means for storing a single-bit for one clock interval as a carry output signal;
and
means for selecting to said third unit-delay means for storage, said current carry bit or carry input signal bit to said cell module.

7 more elements

A method for performing serial-parallel multiplication in electronic apparatus, said method comprising the steps of:

supplying a serial digital multiplier signal having words the n bits of each of which words occur during respective ones of n successive clock intervals with the successive bits in each word increasing in significance, n being an integer greater than one;
supplying k parallel bits representative of a digital multiplicand signal during the n bits of each word of said serial digital multiplier signal, k being an integer greater than one and no larger than n;
successively multiplying the k parallel bits representative of a digital multiplicand signal in a respective AND gate by each bit of said digital multiplier signal to generate respective partial products k bits in width;
accumulating a partial sum in a parallel adder composed of bit slices, as said partial products are generated during said n successive clock intervals, by shifting the previous partial sum, if any, one bit place towards greater significance;
providing in uncombined form a respective sum bit and a respective carry bit from each bit-slice of said parallel adder;
extracting the least significant sum bit of said partial sum each of said n successive clock intervals to generate a minor product serial output signal;
applying the more significant of said sum bits from said parallel adder during the last of said n successive clock intervals to a first parallel-to-serial converter;
applying the carry bits from said parallel adder during the last of said n successive clock intervals to a second parallel-to-serial converter;
supplying, to a serial adder, said sum bits sequentially from said first parallel-to-serial converter and said carry bits sequentially from said second parallel-to-serial converter with one clock interval relative delay, thereby to generate from said serial adder a major product serial output signal.

6 more elements

Dependencies are inferred from the claim text.

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Abstract

A serial-parallel digital multiplier comprising:

means for supplying k bits of a multiplicand signal in parallel during an earlier of two consecutive successions of clock intervals, each n in number, k being an integer greater than one and n being a positive integer at least as large as k;
a battery of two-input port AND gates, k in number, having respective first input ports, respective second input ports, and respective output ports;
means for applying to the first input ports of said battery of AND gates, during each of said earlier succession of clock intervals except its last clock interval, k bits corresponding to respective bits of said multiplicand signal;
means for applying to the first input ports of said battery of AND gates during the last of said earlier succession of clock intervals, k bits that are the one's complement of respective bits of said multiplicand signal;
means for supplying to the second input ports of said battery of AND gates n successive bits of a bit-serial multiplier signal of bit length n as sequentially received during respective ones of said earlier succession of clock intervals, whereby the partial products of each of these bits with the signal applied to the first ports of said AND gates are successively generated at the output ports of said battery of AND gates during respective ones of said earlier succession of clock intervals;
a parallel adder, composed of k bit slices, for adding each successively generated partial product as a first addend to respective second and third addends to generate for each of said k bit slices a respective sum bit and a respective carry bit;
means for supplying during said earlier succession of clock signals a minor product signal obtained from the successive sum bits for the least significant of said k bit slices of said parallel adder;
means for delaying by one clock interval the sum bits generated by the parallel adder for the other, more significant ones of its k bit slices, to generate except for sign bit each successive said second addend for said parallel adder during said earlier succession of clock intervals;
means for applying during the last of said earlier succession of clock intervals a ZERO as the sign bit of said second addend;
means for applying during all other clock intervals in said earlier succession except the first, the sum bit generated in the most significant bit slice of said parallel adder and delayed by one clock interval as the sign bit of said second addend;
means for delaying by one clock interval the carry bits generated by the parallel adder to generate each successive said third addend for said parallel adder during said earlier succession of clock intervals;
first parallel-to-serial converting means for converting the sum bits supplied from said k bit slices of said parallel adder during the last of said earlier succession of clock intervals to appear serially during that clock interval and the ensuing next (k-1) clock intervals in a later of said two consecutive successions of clock intervals, to be followed by a ZERO the next clock interval of said later succession, to be followed by a repeat of the most significant of the sum bits for each remaining one of the n clock intervals of said later succession;
second parallel-to-serial converting means for converting the carry bits supplied from the k bit slices of said parallel adder during the last of said earlier succession of clock intervals to appear serially the ensuing next k clock intervals in said later succession, to be followed by a repeat of the most significant of the carry bits for any remaining one of the n clock intervals of said later succession;
and
a serial adder for adding the sum bits supplied serially by said first parallel-to-serial converting means, the carry bits supplied serially by said second parallel-to-serial converting means, and the sign bit of said bit-serial multiplier signal during the last of said ensuing next k clock intervals of said later succession, thereby to generate a major product signal.

12 more elements