Insulated-gate type transistor and semiconductor integrated circuit using such transistor

An insulted-gate type transistor, comprising:

• a semiconductor body having a first conductivity type and a low impurity concentration and having a main surface;
• a heavily-doped source region formed in said main surface of the semiconductor and having a second conductivity type opposite to said first conductivity type;
• a heavily-doped drain region formed in said main surface of the semiconductor body at a site separate from said source region and having said second conductivity type;
• a subsidiary semiconductor region formed adjacent to and contiguous with the bottom of said source region and having said first conductivity type and an impurity concentration greater than that of said semiconductor body, said subsidiary semiconductor region having a portion extending laterally beyond said source region toward said drain region and another portion exposed at said main surface;
• a source electrode formed on said main surface in contact with both said source region and said subsidiary semiconductor region;
• a channel semiconductor region of said first conductivity type located in said semiconductor body, between said source and drain regions, adjacent to said source region between said main surface and said laterally extending portion of said subsidiary semiconductor region, and having an impurity concentration lower than that in said subsidiary semiconductor region;
• an insulated-gate structure including an insulating layer formed on said channel semiconductor region and a conductive gate electrode formed on said insulating layer;
• and
• said channel region having such dimensions and a resistivity that form a potential barrier between said source and drain regions and that drain current is controlled exponentially by said potential barrier.