US 4,937,738 AGranted

Data processing system which selectively bypasses a cache memory in fetching information based upon bit information of an instruction

AssigneesHitachi, Ltd., Hitachi Microcomputer

InventorsKunio Uchiyama, Atsushi Hasegawa, Takeshi Aimoto, Tadahiko Nishimukai

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Abstract

A cache memory contained in a processor features a high efficiency in spite of its small capacity. In the cache memory control circuit, it is detected whether the access operation of the processor is directed to a particular region of the memory, and when the data is to be read out from, or is to be written onto, the particular region, the data is copied onto the cache memory and when the data is to be read out from other regions, operation of the memory is executed immediately without waiting for the reference of cache memory. By assigning the particular region for the data that is to be used repeatedly, it is possible to provide a cache memory having good efficiency in spite of its small capacity. A representative example of such data is the data in a stack.

Claims9

Dependent claims

A data processing system comprising:

a main memory for storing data;
a microprocessor coupled to said main memory and including a cache memory, the cache memory having a capacity smaller than that of said main memory and operating at a speed faster than that of said main memory, said cache memory being accessed by receipt of addresses and holding a copy of a part of said data stored at locations corresponding to said addresses in said main memory;
wherein said microprocessor further includes a frame pointer for designating an address of a current frame which is accessed during execution of a subroutine, said current frame being in a stack of said data stored in said main memory, and a stack pointer for designating an address of the top of said stack;
wherein instructions are stored in said main memory and executed by said microprocessor, at least some instructions for said microprocessor include bit information which designates whether said instruction calls or does not call for accessing a stack area designated by said frame pointer and said stack pointer;
wherein said microprocessor further includes:
(1) first means for detecting said bit information in an instruction;
and
(2) second means for accessing said cache memory to read out said copy of said part of said data from said cache memory before accessing said main memory in response to a detection result of said first means in case said bit information designates that said instruction calls for accessing said stack area;
and
wherein said second means accesses said main memory to read out a part of said data from said main memory without regard to said cache memory in response to another detection result of said first means in case said bit information designates that said instruction does not call for accessing said stack area.

7 more elements

A microprocessor for use with a main memory in a data processing system, said microprocessor comprising:

a cache memory, the cache memory having a capacity smaller than that of said main memory and operating at a speed faster than that of said main memory, said cache memory being accessed by receipt of addresses and holding a copy of a part of data stored at locations corresponding to said addresses in said main memory;
a frame pointer for designating an address of a current frame which is accessed during a subroutine's execution, said current frame being in a stack of said data stored in said main memory;
and
a stack pointer for designating an address of the top of said stack;
wherein instructions are stored in said main memory and executed by said microprocessor, at least some instructions for said microprocessor include bit information which designates whether said instruction calls or does not call for accessing a stack area designated by said frame pointer and said stack pointer;
and
wherein said microprocessor further includes:
(1) first means for detecting said bit information in an instruction;
and
(2) second means coupled to said cache memory for accessing said cache memory to read out said copy of said part of said data from said cache memory before accessing said main memory for said data in response to a detection result of said first means in case said bit information designates that said instruction calls for accessing said stack area;
and
wherein said second means accesses said main memory to read out data from said main memory without regard to said cache memory in response to another detection result of said first means in case said bit information designates that said instruction does not call for accessing said stack area.

9 more elements

Dependencies are inferred from the claim text.