Integrated analog-to-digital converter
AssigneeMicrochip Technology Incorporated
InventorsDavid Rich, Peter Staley
Life of this patent
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Abstract
A feedback coder, which employs simple CMOS push/pull amplifiers as gain elements, along with a bistable circuit, in its preferred embodiment takes the form of a second-order delta-sigma modulator. The output of the modulator is converted into pulse code modulated words by a finite impluse response filter which incorporates a partial coefficient generator utilizing simplified logic. The generator output is provided to an accumulator in which the stage operate at reduced speed. A simple multiplexer generates a serial output. The entire converter can be integrated on a semiconductor chip of relatively small area.
Claims24
A decimator comprising partial coefficient generator means and a data accumulator means, said generator means comprising input means adapted to receive an input signal, memory means having address means and data output means, counter means and shift register means, said input signal receiving means, the output of said counter means and the output of said shift register means being operably connected to said address means to address said memory to output data to said data output means, said data output means being operably connected to said data accumulator means.
A decimator comprising partial coefficient generator means and a data accumulator means, said generator means comprising input means adapted to receive an input signal, memory means having address means and data output means, counter means and shift register means, said input signal receiving means, the output of said counter means and the output of said shift register means being operably connected to said address means, said data output means being operably connected to said data accumulator means, wherein said data output means generates a parallel output word and wherein said data accumulator means comprises means for delaying each bit of said parallel output word by an interval which is a function of the position of the bit in the output word.
A decimator for use with means for generating timing signals comprising partial coefficient generating means and data accumulator means, said generator means comprising means for receiving an input signal, means for delaying said input signal, and means for combining said input signal, said delayed input signal, and said timing signals to form the bits of a parallel output word, said data accumulator means comprising means for receiving the parallel output word.
A decimator comprising a partial coefficient generator and data accumulator means, said data accumulator means comprising means for delaying each bit of a parallel input word by an interval which is a function of the position of the bit in said word and a plurality of accumulator stages, ech of said stages comprising adder means having first and second data inputs, a clock input, a sum output and a carry output, said first data input of each of said adder means receiving a different bit of said word, means for operably connecting said second data input of each of said adder means with said sum output thereof, and means for operably connecting said clock input of each of said adder means to said carry output of the preceding adder means.
A decimator comprising partial coefficient generator means and a data accumulator means, said generator means comprising input means adapted to receive an input signal, memory means having address means and data output means, counter means and shift register means, said input signal receiving means, the output of said counter means and the output of said shift register means being operably connected to said address means, said data output means being operably connected to said data accumulator means and wherein said counter means comprises a multi-bit counter.
A decimator comprising partial coefficient generator means and a data accumulator means, said generator means comprising input means adapted to receive an input signal, memory means having address means and data output means, counter means and shift register means, said input signal receiving means, the output of said counter means and the output of said shift register means being operably connected to said address means, said data output means being operably connected to said data accumulator means and wherein said shift register means comprises series connected shift registers, each having an output operably connected to said address means.
Dependencies are inferred from the claim text.