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AssigneeKabushiki Kaisha Toshiba
InventorsAkio Nakagawa, Kaoru Imamura, Ryo Sato, Tadahide Hoshi
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A method of manufacturing a semiconductor device comprising the steps of bringing a mirror-polished surface of a first semiconductor substrate of a first conductivity type into contact with a mirror-polished surface of a second semiconductor substrate of a second conductivity type having an impurity concentration which is lower than that of said first conductivity type, in a clean atmosphere, and thermally heating said first and second semiconductor substrates so that they unite. Impurity is diffused from said first semicondutor substrate into said second semiconductor substrate, thereby forming a diffusion layer of a first conductivity type in said second semiconductor substrate. A total amount of impurity of said diffusion layer is 1.times.10.sup.13 /cm.sup.2 to 2.times.10.sup.15 /cm.sup.2, to form a pn junction in said second semiconductor substrate.
A method of manufacturing a semiconductor device, comprising the steps or bringing a mirror-polished surface of a first silicon substrate of a first conductivity type into contact with a mirror-polished surface of an ion-implanted layer of a second conductivity type formed in a second silicon substrate of a second conductivity type which contains an impurity concentration lower than that of said first conductivity type and that contained in said ion-implanted layer, in a clean atmosphere, to unite said first and silicon substrates, and heating the united substrates at a temperature of 200.degree. C. or more, but less than 1200.degree. C., and for a time sufficient to diffuse an impurity from said silicon substrate into said second ion-implanted layer, thereby forming a diffusion layer of a first conductivity type having an impurity concentration of 1.times.10.sup.13 /cm.sup.2 to 2.times.10.sup.15 /cm.sup.2 in said second silicon substrate, said diffusion layer having a thickness of 6 .mu.m or less and forming a pn junction in said second silicon substrate.
A method of manufacturing a semiconductor device, comprising the steps of bringing a mirror-polished surface of a first silicon substrate of a first conductivity type into contact with a mirror-polished surface of a second silicon substrate of a second conductivity type having a lower impurity concentration than that of said first conductivity type, in a clean atmosphere without any thermal fusion, and thermally heating said first and second silicon substrates at a temperature of 200.degree. C. or more, but less than 1200.degree. C., and for a time sufficient so that their bonding strength increased and an impurity is diffused from said first silicon substrate into said second silicon substrate, thereby to form a diffusion layer of a first conductivity type and a pn junction in said second silicon substrate, said diffusion layer having a thickness of 6 .mu.m or less and an impurity concentration of said diffusion layer being 1.times.10.sup.13 /cm.sup.2 to 2.times.10.sup.15 /cm.sup.2.
A method of manufacturing a semiconductor device, comprising the steps of bringing a mirror-polished surface of a first silicon substrate of a first conductivity type and having a resistivity of 0.01 to 0.05.OMEGA..multidot.cm into contact with a mirror-polished surface of an ion-implanted layer of a second conductivity type formed in a second silicon substrate of a second conductivity type which contains an impurity concentration lower than that of said first conductivity type and that contained in said ion-implanted layer, in a clean atmosphere, to unite said first and silicon substrates, and heating the united substrates at a temperature of 200.degree. C. or more, but less than 1200.degree. C., and for a time sufficient to diffuse an impurity from said first silicon substrate into said second ion-implanted layer, thereby forming a diffusion layer of a first conductivity type having an impurity concentration of 1.times.10.sup.13 /cm.sup.2 to 2.times.10.sup.15 /cm.sup.2 in said second silicon substrate, said diffusion layer having a thickness of 3 to 7 .mu.m and forming a pn junction in said second silicon substrate.
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