US 4,933,846 AGranted

Network communications adapter with dual interleaved memory banks servicing multiple processors

AssigneeNetwork Systems Corporation

InventorsDonald J. Humphrey, James P. Hughes, Wayne A. Peterson, Wayne R. Roiger

Life of this patent

Estimating the term…

Loading patent…

Abstract

A network communications adapter interconnects a plurality of digital computing resources for mutual data exchange in which a high performance, large capacity common memory is provided with a pair of external buses which allows multiple processors to store information in and read information from the common memory. The common memory is configured into two banks, each bank operating independently and concurrently under control of bus switching logic with separate address, control and data buses. The common memory typically provides 400 megabits per second of bandwidth to the multiple attached thirty-two and sixteen bit processors which may be coupled either to both buses simultaneously or individually to the two buses. The bus switching logic then allocates all of the available bandwidth to the individual processors coupled to the buses based upon a predetermined profile established at the time of system installation. Also included in the bus switch logic is circuitry for broadcasting a processor I.D., whereby only a particular processor assigned the same identifier will be afforded an access slot time during which communication over the dual bus structure can take place. One of the interconnected processors is designated as the node controller and it includes circuitry and software for implementing interprocessor interrupt handling and storage protection functions. Others of the plurality of processors coupled to the two memory buses provided input/output interfaces for host computers, digital peripheral devices, communications trunks or buses, or to wireless links for more remote communication.

Claims4

Dependent claims

A communications network adapter comprising:

(a) central random access buffer memory means for storing data at addressable locations, said buffer memory means being partitioned into first and second independently and concurrently operating interleaved banks;
(b) first and second common bus means selectively connectable on an alternating basis to said first and second banks for providing, on a time multiplexed basis, address representing signals and data representing signals to said buffer memory means for storing said data representing signals therein;
(c) first and second read data bus means selectively connectable on an alternating basis to said two banks for carrying data representing signals read out from the memory locations in said buffer memory means specified by said address representing signals carried by said first and second common bus means, each of said first and second common bus means and read data bus means having a finite bandwidth measurable in bits per second;
(d) a plurality of processing means comprising nodes individually coupled to said first and second common buses and to said read data buses, certain ones of said plurality of processing means having input/output means for communication with digital devices connected thereto;
and
(e) node control means coupled to said first and second common bus means and to said first and second read data bus means, said node control means including memory access control means for synchronously and cyclically connecting alternate ones of said first and second banks to said first and second common bus means and said first and second read data bus means, said node control means further including broadcast means for broadcasting a processor slot I.D. number to each of said plurality of processing means, said broadcast means having programmable read-only memory slot means for storing a plurality of processor I.D. words defining system profiles, addressing means including counter means and preset switching means coupled to said programmable read-only memory for reading out said words defining system profiles as said counter means is advanced, clock signal generating means for applying regularly occurring timing signals to said counter means to sequentially advance said counter means to read out processor slot I.D. words from said programmable read-only memory in a desired sequence, and a processor slot I.D. bus coupling said processor I.D. words from said programmable read-only memory means to said plurality of processing means, and means for selectively assigning access time slots to said plurality of processing means so that the total aggregate bandwidth of said first and second common bus means and read data bus means is allocated to said plurality of processing means on a predetermined, non-conflicting, need basis.

3 more elements

A communications network adapter comprising:

(a) central random access buffer memory means for storing data at addressable locations, said buffer memory means being partitioned into first and second independently and concurrently operating interleaved banks;
(b) first and second common bus means selectively connectable on an alternating basis to said first and second banks for providing, on a time multiplexed basis, address representing signals and data representing signals to said buffer memory means for storing and data representing signals therein;
(c) first and second read data bus means selectively connectable on an alternating basis to said two banks for carrying data representing signals read out from the memory locations in said buffer memory means specified by said address representing signals carried by said first and second common bus means, each of said first and second common bus means and read data bus means having a finite bandwidth measurable in bits per second;
(d) a plurality of processing means comprising nodes individually coupled to said first and second common buses and to said read data buses, certain ones of said plurality of processing means having input/output means for communication with digital devices connected thereto;
(e) node control means coupled to said first and second common bus means and to said first and second read data bus means, said node control means including memory access control means for synchronously and cyclically connecting alternate ones of said first and second banks to said first and second common bus means and said first and second read data bus means, said node control means further including broadcast means for broadcasting a processor slot I.D. number to each of said plurality of processing means, said broadcast means having programmable read-only memory slot means for storing a plurality of processor I.D. words defining system profiles, addressing means including counter means and preset switching means coupled to said programmable read-only memory for reading out said words defining system profiles as said counter means is advanced, clock signal generating means for applying regularly occurring timing signals to said counter means to sequentially advance said counter means to read out processor slot I.D. words from said programmable read-only memory in a desired sequence, and a processor slot I.D. bus coupling said processor I.D. words from said programmable read-only memory means to said plurality of processing means;
and means for selectively assigning access time slots to said plurality of processing means so that the total aggregate bandwidth of said first and second common bus means and read data bus means is allocated to said plurality of processing means on a predetermined, non-conflicting, need basis;
and
(f) interrupt control means in said node control means for generating a timed sequence of interrupt identifier codes with interrupt bus means coupling said interrupt control means to said plurality of processing means for transmitting said interrupt identifier codes to each of said plurality of processing means, means in each of said processing means for decoding a different one of said interrupt identifier codes assigned to it for allowing any of the plurality of processing means responding to its interrupt identifier code to place on said interrupt bus means an interrupt request and a processor identifier code for identifying a destination processor to which said interrupt request is directed, and interrupt processor means coupled to said interrupt bus means for receiving said interrupt requests and said processor identifier codes of the destination processors for routing interrupt data to identified ones of said plurality of destination processors in accordance with a predetermined priority assignment.

5 more elements

Dependencies are inferred from the claim text.