Integrated circuit with clock generator

An integrated circuit comprising:

• clock signal generator means for receiving a reference frequency signal and for generating a clock signal of a first predetermined frequency in response to the reference frequency signal;
• wherein the improvement comprises:
• loss of reference signal detect means for receiving the reference frequency signal and for producing a loss of reference output signal in response to a predetermined condition of the reference frequency signal;
• and
• the clock signal generator means being responsive to the loss of reference output of the loss of reference signal detect means for generating a clock signal of a second frequency different from the first predetermined frequency.

A phase-locked loop frequency generator circuit comprising:

• oscillator circuit means for producing a reference signal of a first frequency at an output thereof;
• a voltage-controlled oscillator having a control voltage input and an oscillator output;
• a frequency divider circuit having an input coupled to the oscillator output of the voltage-controlled oscillator and an output;
• a phase comparator circuit having inputs coupled to output of the oscillator circuit means and the output of the frequency divider circuit and a phase error output;
• a loop filter circuit having an input coupled to the phase error output of the phase comparator circuit and a control voltage output coupled to the control voltage input of the voltage controlled oscillator;
• wherein the improvement comprises:
• a loss of reference signal detect circuit having an input coupled to the output of the oscillator circuit and a reference enable output;
• voltage reference means for producing a voltage reference signal;
• and
• switch means for responding to the reference enable output of the loss of reference signal detect circuit by substituting the voltage reference signal for the control voltage output of the loop filter circuit as the control voltage input of the voltage controlled oscillator.

An apparatus for receiving an oscillator signal and for detecting a loss of the oscillator signal comprising:

• a first input coupled to a source of the oscillator signal;
• a second input coupled to a source of a clock signal;
• a first shift register comprising an input coupled to the first input and a first plurality of stages, each of said first plurality of stages having a clock input coupled to the second input and an output;
• first logic means having an input coupled to the first input for inverting the oscillator signal;
• a second shift register comprising an input coupled to the first logic means and a second plurality of stages, each of said second plurality of stages having a clock input coupled to the clock signal and an output;
• second logic means having inputs coupled to said outputs of each of said stages of said first shift register for producing a first loss signal when all of said outputs are in a predetermined logic state;
• third logic means having inputs coupled to said outputs of each of said stages of said second shift register for producing a second loss signal when all of said outputs are in a predetermined logic state;
• and
• fourth logic means having inputs coupled to receive said first and second loss signals for producing a loss of oscillator signal when either of said first and second loss signals is received.

In an integrated circuit comprising a clock signal generator circuit which receives an oscillator signal and produces a clock signal, a loss of oscillator circuit comprising:

• first logic means coupled to receive the oscillator signal for producing an inverted oscillator signal;
• a first shift register comprising an input coupled to receive the oscillator signal and a first plurality of stages, each of said first plurality of stages comprising a clock input coupled to receive the clock signal, a reset input coupled to receive the inverted oscillator signal and an output;
• a second shift register comprising an input coupled to receive the inverted oscillator signal and a second plurality of stages, each of said second plurality of stages comprising a clock input coupled to receive the clock signal, a reset input coupled to receive the oscillator signal and an output;
• second logic means comprising a first plurality of inputs coupled to said outputs of said first plurality of stages for producing a first loss signal;
• third logic means comprising a second plurality of inputs coupled to said outputs of said second plurality of stages for producing a second loss signal;
• and
• fourth logic means comprising inputs coupled to said second and third logic means for producing a loss of oscillator signal.

An apparatus for receiving an oscillator signal and for detecting a loss of the oscillator signal comprising:

• a first input coupled to a source of the oscillator signal;
• a second input coupled to a source of a clock signal;
• a first shift register comprising an input coupled to the first input and a first plurality of stages, each of said first plurality of stages having a clock input coupled to the second input and an output;
• first logic means having an input coupled to the first input for inverting the oscillator signal;
• a second shift register comprising an input coupled to the first logic means and a second plurality of stages, each of said second plurality of stages having a clock input coupled to the clock signal and an output;
• second logic means having inputs coupled to said outputs of each of said stages of said first shift register for producing a first loss signal when all of said outputs are in a predetermined logic state;
• third logic means having inputs coupled to said outputs of each of said stages of said second shift register for producing a second loss signal when all of said outputs are in a predetermined logic state;
• fourth logic means having inputs coupled to receive said first and second loss signals for producing a loss of oscillator signal when either of said first and second loss signals is received;
• and
• a third input coupled to the output of one of said first plurality of stages and one of said second plurality of stages for reducing the number of clock signal periods required to produce said loss of oscillator signal.